- ad6157e timestamps: Rename timestamps to make names more consistent by Jakub Czapiga · 2 years, 5 months ago
- 73e0f18 soc/amd/cezanne: Move APOB update into ramstage by Raul E Rangel · 3 years ago
- 5c124a9 soc/amd/{cezanne,picasso}: Add TS_START_ROMSTAGE by Raul E Rangel · 3 years, 1 month ago
- 54888e8 Revert "soc/amd/cezanne: Add support to perform early EC sync" by Karthikeyan Ramasubramanian · 3 years, 3 months ago
- 31f7a72 soc/amd/cezanne: save chipset state to CBMEM by Martin Roth · 3 years, 4 months ago
- ad7c33a soc/amd/cezanne: Add support to perform early EC sync by Karthikeyan Ramasubramanian · 3 years, 3 months ago
- 2421de6 soc/amd/cezanne: factor out UPD-M configuration from romstage by Felix Held · 3 years, 3 months ago
- 9a6bc07 soc/amd/cezanne: select common APOB NV cache code by Felix Held · 3 years, 4 months ago
- b825acb soc/amd/cezanne: Disable legacy DMA IO ports by Raul E Rangel · 3 years, 4 months ago
- ec098b5 soc/amd: only print CPU family and model in bootblock by Felix Held · 3 years, 4 months ago
- b9e8044 soc/amd/cezanne/romstage: Store early dram region by Raul E Rangel · 3 years, 5 months ago
- c86acf4 soc/amd/cezanne: populate some FSP-M UPDs by Felix Held · 3 years, 5 months ago
- ffc87e9 soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls by Felix Held · 3 years, 5 months ago
- 57419de soc/amd/cezanne: add basic romstage by Felix Held · 3 years, 6 months ago
- 8d0a609 soc,vendorcode/amd/cezanne: add basic FSP integration by Felix Held · 3 years, 6 months ago
- dc2d356 soc/amd/cezanne: add skeleton for new SoC by Felix Held · 3 years, 7 months ago