- ad12b4f soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization by Chris.Wang · 1 year, 8 months ago
- 9ac0984 soc/amd/mendocino: add dptc tablet mode support by Chris.Wang · 1 year, 8 months ago
- f7a0927 soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles by EricKY Cheng · 1 year, 10 months ago
- b3b27f7 soc/amd/mendocino: Enable GPP clk req disabling for disabled devices by Robert Zieba · 1 year, 11 months ago
- 1cf0acd soc/amd/mendocino: Add low/no battery VRM limit registers by Tim Van Patten · 1 year, 11 months ago
- b06873f soc/amd/mendocino: Add VRM limit DPTC registers by Tim Van Patten · 2 years ago
- 53ba14d amd/mendocino: Control DPTC with only Kconfig by Tim Van Patten · 1 year, 11 months ago
- b4b85eb soc/amd: Remove unsupported DPTC tablet mode settings by Tim Van Patten · 2 years ago
- 9244358 soc/amd: Refactor DPTC Tablet Mode by Tim Van Patten · 2 years ago
- 9f1588c amd: Convert dptc_enable to bool by Tim Van Patten · 2 years ago
- 665476d soc/amd/mendocino: enable CPPC feature by Felix Held · 2 years ago
- 4f73242 treewide: Rename Sabrina to Mendocino by Jon Murphy · 2 years ago[Renamed (94%) from src/soc/amd/sabrina/chip.h]
- a05f518 soc/amd/sabrina: only make the available clock outputs configurable by Felix Held · 2 years, 2 months ago
- 556d1cc soc/amd/*/i2c: factor out common I2C pad configuration by Felix Held · 2 years, 6 months ago
- cbf290c soc/amd/sabrina: drop CPPC code by Felix Held · 2 years, 7 months ago
- 3c44c62 soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne by Felix Held · 2 years, 7 months ago