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review.coreboot.org / coreboot / ac9590395e0404e1fa1199643a1b28b228f992e5 / src / northbridge / intel / x4x / raminit_ddr23.c
  1. ac95903 treewide: replace GPLv2 long form headers with SPDX header by Patrick Georgi · 4 years, 2 months ago
  2. 02363b5 treewide: Move "is part of the coreboot project" line in its own comment by Patrick Georgi · 4 years, 2 months ago
  3. f3f36fa src (minus soc and mainboard): Remove copyright notices by Patrick Georgi · 4 years, 4 months ago
  4. ef90609 src: capitalize 'RAM' by Elyes HAOUAS · 4 years, 5 months ago
  5. 68ec3eb src: Move 'static' to the beginning of declaration by Elyes HAOUAS · 5 years ago
  6. 8bb2bac nb/intel/x4x/raminit: Move dummy reads after JEDEC init by Arthur Heymans · 5 years ago
  7. 5033d6c nb/intel/x4x: Die on invalid memory speeds by Jacob Garber · 5 years ago
  8. e951e8e nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} by Elyes HAOUAS · 5 years ago
  9. c53665c nb/intel/x4x: Remove variable set but not used by Elyes HAOUAS · 5 years ago
  10. cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
  11. 13f6650 device/mmio.h: Add include file for MMIO ops by Kyösti Mälkki · 5 years ago
  12. f1b58b7 device/pci: Fix PCI accessor headers by Kyösti Mälkki · 5 years ago
  13. 586f24d northbridge: Remove unneeded include <pc80/mc146818rtc.h> by Elyes HAOUAS · 6 years ago
  14. 0ce41f1 src: Add required space after "switch" by Elyes HAOUAS · 6 years ago
  15. d2b9ec1 src: Remove unneeded include "{arch,cpu}/cpu.h" by Elyes HAOUAS · 6 years ago
  16. d522db0 nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware by Arthur Heymans · 6 years ago
  17. 3a2f900 x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] by Felix Held · 6 years ago
  18. 432575c x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2] by Felix Held · 6 years ago
  19. 7345a17 nb/intel/x4x: Fix a few things in set_enhanced_mode by Arthur Heymans · 6 years ago
  20. 0602ce6 nb/intel/x4x: Add the option for stacked channel map settings by Arthur Heymans · 6 years ago
  21. 0d28495 nb/intel/x4x: Adapt post JEDEC for DDR3 by Arthur Heymans · 7 years ago
  22. 3fa103a nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings by Arthur Heymans · 7 years ago
  23. b4a7804 nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings by Arthur Heymans · 7 years ago
  24. b5170c3 nb/intel/x4x: Implement write leveling by Arthur Heymans · 7 years ago
  25. f128726 nb/intel/x4x: Add DDR3 JEDEC init by Arthur Heymans · 7 years ago
  26. e6cc21e nb/intel/x4x/raminit: DDR3 specific ODT by Arthur Heymans · 7 years ago
  27. 0d1c9b0 nb/intel/x4x: Add DDR3 rcomp by Arthur Heymans · 7 years ago
  28. 638240e nb/intel/x4x/raminit: Support programming initials DD3 DLL setting by Arthur Heymans · 7 years ago
  29. 66a0f55 nb/intel/x4x/raminit: Support programming DDR3 timings by Arthur Heymans · 7 years ago
  30. 7a3a319 nb/intel/x4x/raminit: Make programming launch ddr3 specific by Arthur Heymans · 7 years ago
  31. 840c27e nb/intel/x4x/raminit: Make programming crossclock support DDR3 by Arthur Heymans · 7 years ago
  32. a2cc231 nb/intel/x4x: Rename a things that are not specific to DDR2 by Arthur Heymans · 7 years ago[Renamed (97%) from src/northbridge/intel/x4x/raminit_ddr2.c]
  33. 701da39 nb/intel/x4x/raminit: Fix programming dual channel registers by Arthur Heymans · 7 years ago
  34. 16a70a4 nb/intel/x4x: Change memory layout to improve MTRR by Arthur Heymans · 7 years ago
  35. dfce932 nb/intel/x4x: Fix programming CxDRB by Arthur Heymans · 7 years ago
  36. 95c48cb nb/intel/x4x: Implement both read and write training by Arthur Heymans · 7 years ago
  37. 276049f nb/intel/x4x: Add a convenient macro to loop over bytelanes by Arthur Heymans · 7 years ago
  38. 1994e448 nb/intel/x4x: Clarify the raminit memory mapping by Arthur Heymans · 7 years ago
  39. 0bf87de nb/intel/x4x: Refactor setting default dll settings by Arthur Heymans · 7 years ago
  40. adc571a nb/intel/x4x: Use SPI flash to cache raminit results by Arthur Heymans · 7 years ago
  41. 7be74db nb/x4x/raminit_ddr2: Refactor clock configuration slightly by Jonathan Neuschäfer · 6 years ago
  42. 3cf9403 nb/x4x/raminit: Rewrite SPD decode and timing selection by Arthur Heymans · 7 years ago
  43. 24798a1 nb/intel/x4x: Fix booting with FSB800 DDR667 combination by Arthur Heymans · 7 years ago
  44. 6d7a8c1 nb/intel/x4x/raminit: Rework receive enable calibration by Arthur Heymans · 7 years ago
  45. 3876f24 nb/intel/x4x: Rework programming DQ and DQS DLL timings by Arthur Heymans · 7 years ago
  46. 349e085 sb/intel/i82801jx: Add correct PCI ids and change names by Arthur Heymans · 7 years ago
  47. 37689fa nb/intel/x4x/raminit: Initialise async variable by Arthur Heymans · 7 years ago
  48. 27f0ca1 nb/intel/x4x: Use a struct for dll settings instead of an array by Arthur Heymans · 7 years ago
  49. cfa2eaa nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUP by Arthur Heymans · 7 years ago
  50. e729366 nb/intel/x4x/raminit: Remove very long delay by Arthur Heymans · 7 years ago
  51. ddc8828 nb/x4x/raminit.c: Remove ME locking code by Arthur Heymans · 7 years ago
  52. bb5e77c nb/x4x: Move checkreset before SPD reading by Arthur Heymans · 8 years ago
  53. 70a1dda nb/intel/x4x: Fix issues found by checkpatch.pl by Arthur Heymans · 7 years ago
  54. ef7e98a nb/intel/x4x: Implement resume from S3 suspend by Arthur Heymans · 8 years ago
  55. 97e13d8 nb/intel/x4x: Fix raminit on reset path by Arthur Heymans · 8 years ago
  56. eee4f6b nb/x4x/raminit: Fix programming dram timings by Arthur Heymans · 8 years ago
  57. 128c104 nb/intel: Fix some spelling mistakes in comments and strings by Martin Roth · 8 years ago
  58. 8a3514d nb/x4x/raminit.c: Improve crossclock table cosmetics by Arthur Heymans · 8 years ago
  59. 523e90f nb/intel/x4x: Increase MMIO PCI space to 2GiB by Damien Zammit · 8 years ago
  60. 12df950 northbridge/intel: Add required space before opening parenthesis '(' by Elyes HAOUAS · 8 years ago
  61. 27f94ee x4x: add non documented vram sizes by Arthur Heymans · 8 years ago
  62. 7c2e539 nb/intel/x4x: Fix CAS latency detection and max memory detection by Damien Zammit · 8 years ago
  63. 68e1dcf nb/intel/x4x: Fix unpopulated value by Damien Zammit · 8 years ago
  64. d63115d nb/intel/x4x: Tidy up raminit and fix msbpos() function by Damien Zammit · 8 years ago
  65. 9fb08f5 nb/intel/x4x: Fix memory hole with both channels populated by Damien Zammit · 8 years ago
  66. cbe3892 northbridge/intel/x4x: clean up includes by Martin Roth · 9 years ago
  67. 4b513a6 northbridge/intel/x4x: Native raminit by Damien Zammit · 9 years ago