- a91c919 soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress by Sridhar Siricilla · 4 years ago
- c25c1eb src: Update bare access to BOOL CONFIG_ vals to CONFIG() by Martin Roth · 4 years, 1 month ago
- 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
- e01054d soc/intel/cannonlake: Add DisableHeciRetry to config by Christian Walter · 4 years, 4 months ago
- b2f8ce7 soc/intel/cannonlake: Steal no memory for disabled IGD by Christian Walter · 4 years, 5 months ago
- f5627e8 soc/intel/cannonlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 4 months ago
- 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
- c004857da soc/intel/cannonlake: Add chip config for SATA strength by Jamie Chen · 4 years, 7 months ago
- e1470ea soc/intel/cannonlake: Add chip config to override CPU flex ratio by Subrata Banik · 4 years, 9 months ago
- 7736bfc soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig by Michael Niewöhner · 4 years, 10 months ago
- 8950cfb soc/intel: Use config_of() by Kyösti Mälkki · 5 years ago
- 903b40a soc/intel: Replace uses of dev_find_slot() by Kyösti Mälkki · 5 years ago
- 4821a0e soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE by Arthur Heymans · 5 years ago
- 2973d1e vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155 by Aamir Bohra · 5 years ago
- 1159a16 soc/intel/cnl: Enable VT-d by John Zhao · 5 years ago
- c338507 soc/{amd,intel}/chip: Use local include for chip.h by Elyes HAOUAS · 5 years ago
- 3717256 soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig by Kane Chen · 5 years ago
- 7f1a0e6 Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" by Lijian Zhao · 5 years ago
- 250dfc0 soc/intel/cannonlake: Configure Vmx support using Kconfig by Ronak Kanabar · 5 years ago
- 41dad28 soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML by Subrata Banik · 5 years ago
- 68890b9 soc/intel/cannonlake: Update CPU Ratio base on MSR by Lijian Zhao · 5 years ago
- cf32fd1 soc/intel/common: Remove common chip config use_fsp_mp_init by Subrata Banik · 6 years ago
- bfe4a59 soc/intel/cannonlake: Pass coreboot debug interface info to FSP by Maulik V Vaghela · 5 years ago
- cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
- 6527b1a soc/intel/cannonlake: Add Whiskeylake SoC kconfig by Subrata Banik · 6 years ago
- 52b5b58 soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery by Duncan Laurie · 6 years ago
- 0bc3e3d soc/intel/cannonlake: Enable/Disable IPU based on devicetree switch by V Sowmya · 6 years ago
- 3ef7449 soc/intel/cannonlake: Auto turn on HDA controller by Lijian Zhao · 6 years ago
- fd02ff0 soc/intel/cannonlake: Enable CPU flexible ratio by Lijian Zhao · 6 years ago
- 25b387a soc/intel/cannonlake: Remove SmbusEnable by Duncan Laurie · 6 years ago
- fe701ee soc/intel/cannonlake: Enable ISH from device by Lijian Zhao · 6 years ago
- 521e48c soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions by praveen hodagatta pranesh · 6 years ago
- e26c4a4 soc/intel/cannonlake: Add new cannon lake PCH-H support by praveen hodagatta pranesh · 6 years ago
- 742c6fe soc/intel/cannonlake: Move the FSP related callbacks to separate files by Rizwan Qureshi · 6 years ago