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review.coreboot.org / coreboot / a4ffe8aa4981130b240eee5ed22c5bbfa1c7598b / src / northbridge / amd / amdmct
  1. bbd2647 northbridge/amd/amdmct: Honor MMCONF_BASE_ADDRESS by Timothy Pearson · 9 years ago
  2. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  3. 620fa5f northbridge/amd/amdfam10: Collect DIMM information for ramstage use by Timothy Pearson · 9 years ago
  4. d5c82af northbridge/amd/amdmct: Pack MCT and DCT info structs by Timothy Pearson · 9 years ago
  5. b6fa61a northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later by Timothy Pearson · 9 years ago
  6. 226fc94 northbridge/amd/amdmct: Add revision D to K10 revision mask list by Timothy Pearson · 9 years ago
  7. 2b1bcc1 northbridge/amd/amdfam10: Remove Kconfig memory controller options by Timothy Pearson · 9 years ago
  8. 3c20678 northbridge/amd/amdfam10: Fold back memory frequency based on MCT load by Timothy Pearson · 9 years ago
  9. 2012b81 northbridge/amd/amdmct: Fix FTBFS with node interleaving enabled by Timothy Pearson · 9 years ago
  10. 068ca9c northbridge/amd/amdmct: Allow override of memory settings via NVRAM by Timothy Pearson · 9 years ago
  11. 5ec1153 northbridge/amd: Add Kconfig options for ECC redirection by Timothy Pearson · 9 years ago
  12. 6f2caa0 northbridge/amd: Add Kconfig options for ECC scrub rate by Timothy Pearson · 9 years ago
  13. f4cb412 northbridge/amd: Doxygen fixes by Martin Roth · 9 years ago
  14. 65b72ab northbridge: Drop print_ implementation from non-romcc boards by Stefan Reinauer · 9 years ago
  15. 0f92f63 Uniformly spell frequency unit symbol as Hz by Elyes HAOUAS · 9 years ago
  16. 1631c88 northbridge/amd: Remove trailing whitespace by Elyes HAOUAS · 9 years ago
  17. 234781e northbridge: Trivial - drop trailing blank lines at EOF by Edward O'Callaghan · 9 years ago
  18. 68a56ca northbridge/amd/amdmct: Incorrect usage of logical over bitwise and by Edward O'Callaghan · 10 years ago
  19. ba363d3 northbridge/amd/amdmct: Superfluous parenthesis in if-statements by Edward O'Callaghan · 10 years ago
  20. 72ae4a3 northbridge/amd/amdmct/mct: Initialize variables at the eol by Edward O'Callaghan · 10 years ago
  21. 029aaf6 x86: add common definitions for control registers by Aaron Durbin · 10 years ago
  22. d26da9c Coding style: punctuation cleanup [1/2]. by Idwer Vollering · 10 years ago
  23. 42409e8 northbridge/amd/amdmct: Use `static const` instead of `const static` by Paul Menzel · 11 years ago
  24. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  25. f8f0062 Some more #if cleanup by Patrick Georgi · 12 years ago
  26. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  27. 067d223 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. by Marc Jones · 12 years ago
  28. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 12 years ago
  29. 328a694 AMD CPU and chipset fixes for compilation with gcc 4.6 by Stefan Reinauer · 12 years ago
  30. 8eb4273 Add AMD Family 10h PH-E0 support by QingPei Wang · 12 years ago
  31. 471f103 This patch sets max freq defaults for ddr2 and ddr3for fam10. by Marc Jones · 13 years ago
  32. 2ca2f17 Add AMD C32 support. It is based on other existing Fam10 code. by Zheng Bao · 13 years ago
  33. c313210 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  34. 19245c9 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  35. e485aa4 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  36. 0e5d3e1 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  37. adb23a5 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  38. dd676dd For Cx, each ChipSel need to be sent MR command. by Zheng Bao · 13 years ago
  39. a7296e7 The code is tested on my board with register DIMMs. More tests need to be by Zheng Bao · 13 years ago
  40. 69436e1 Fix some settings fo AMD MCT. It is based on BIOS test suite. by Zheng Bao · 13 years ago
  41. ea62e9b More explicite and straight way to set seed. by Zheng Bao · 13 years ago
  42. f3cce2f MTRR related improvements for AMD family 10h and family 0Fh systems by Scott Duplichan · 13 years ago
  43. 8912285 Trivial. Clean up code and add some comments. by Zheng Bao · 13 years ago
  44. 53b52f3 Trivial. Spell checking. by Zheng Bao · 13 years ago
  45. 1dcf6689 Trivial. Spell checking. by Zheng Bao · 13 years ago
  46. c3af12f Trivial. Spell checking. by Zheng Bao · 13 years ago
  47. 3d682fe Trivial. Fix the typo. by Zheng Bao · 13 years ago
  48. 52000e1 Trivial. Re-indent the code. by Zheng Bao · 13 years ago
  49. 7b1a3c3 Trivial. re-Indent the code. by Zheng Bao · 13 years ago
  50. 7cdf1ec Obviously missing brackets. by Xavi Drudis Ferran · 13 years ago
  51. 0c51ddd Complete the code which was missing. by Zheng Bao · 13 years ago
  52. 951a0fe Fix the typo. Field DisAutoRefresh is in DramTimngHi. by Zheng Bao · 13 years ago
  53. d6689ed Please find appended. This patch gets rid of the %gs magic altogether, by Arne Georg Gleditsch · 13 years ago
  54. e150e9a Also improve boot time on AMD for the DDR3 code path. Fix a typo, too. by Arne Georg Gleditsch · 13 years ago
  55. 6556534 Apparently, it's not crucial to clear this at the exact moment we switch by Arne Georg Gleditsch · 13 years ago
  56. f7a999a Trivial. Currently the max frequency is preset as 400Mhz. We need to set a by Zheng Bao · 13 years ago
  57. 08c92e0 AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. by Kerry She · 13 years ago
  58. 9fae99f Get Byte65/66 for register manufacture ID code. RegMan1Present will by Zheng Bao · 13 years ago
  59. 819ee74 Multi-DIMMS on AMD ddr2 MCT channel B fixed. by Kerry She · 13 years ago
  60. 99cfa1e Multi-DIMMS on AMD ddr3 MCT channel B works. by Kerry She · 13 years ago
  61. 108d30b Trivial syntax correction of AMD mct_ddr3 dir. by Kerry She · 13 years ago
  62. 4793ef1 documented workaround erratum 414, see by Xavi Drudis Ferran · 13 years ago
  63. 213ab94 documented workaround erratum 372, see by Xavi Drudis Ferran · 13 years ago
  64. cc6244a Include RB_C3 in erratum 346 by Xavi Drudis Ferran · 13 years ago
  65. 752f1b4 Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc. by Xavi Drudis Ferran · 13 years ago
  66. 6f57b51 Fix all warnings in the tree by Stefan Reinauer · 13 years ago
  67. 817d754 get rid of even more fam10 and k8 warnings. by Stefan Reinauer · 13 years ago
  68. 3d5bb23 Move includes to where they are needed. This allows to simplify by Patrick Georgi · 14 years ago
  69. ad894c5 Get rid of a few more warnings. by Myles Watson · 14 years ago
  70. 14e2277 Since some people disapprove of white space cleanups mixed in regular commits by Stefan Reinauer · 14 years ago
  71. 3173d8c Trivial. Fix a space to tab. by Zheng Bao · 14 years ago
  72. eb75f65 DDR3 support for AMD Fam10. by Zheng Bao · 14 years ago
  73. d653211 zero warnings days: unify mp tables. fix warnings. by Stefan Reinauer · 14 years ago
  74. 075fbe8 Remove a few more warnings from fam10. by Myles Watson · 14 years ago
  75. 97b21be fix a case where the fam10 code would overwrite parts of a struct. by Stefan Reinauer · 14 years ago
  76. 4bcfb09 HWHoleSz must be u32... by Stefan Reinauer · 14 years ago
  77. 3063432 zero warnings days. by Stefan Reinauer · 14 years ago
  78. 362db61 Cosmetically make init_cpus more similar for fam10 and K8. by Myles Watson · 14 years ago
  79. c02b4fc printk_foo -> printk(BIOS_FOO, ...) by Stefan Reinauer · 14 years ago
  80. bc259d0 The following patch implements Opteron Fam 10 rev D (aka Istanbul) by Arne Georg Gleditsch · 14 years ago
  81. fd9c9b8 Use the coreboot pci config read/write functions instead of direct cf8/cfc by Marc Jones · 14 years ago
  82. 1476a9e Without this patch, if we only got a DIMM in Channel B, memory can not be by Zheng Bao · 14 years ago
  83. bab2bef This patch is about the DA-C2 and RB-C2. Chip with install processor by Zheng Bao · 14 years ago
  84. 69a031c The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instead of by Zheng Bao · 14 years ago
  85. b17f952 This is an obvious bug which I overlooked when I worked on the AM2r2 modules. by Zheng Bao · 14 years ago
  86. db8b411 Add AMD family 10 AM2r2 support. by Zheng Bao · 14 years ago
  87. a774192 Fix for Erratum 350 for AMD Fam10h CPUs. by Marco Schmidt · 15 years ago
  88. 99fd2a3 Update equivalent processor revision ID to load latest microcode patches and by Marc Jones · 15 years ago
  89. ce00f1d Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de> by Stefan Reinauer · 15 years ago
  90. c3ec1ac Memory initialization support for AMD Fam10 B3 (B0-B2 already supported). by Marc Jones · 15 years ago
  91. 65e0804 Remove inline from FAM10 CPU initialization functions. by Marc Jones · 16 years ago
  92. da4ce6b Add early MSR and PCI register initialization. by Marc Jones · 16 years ago
  93. e3aeb93 Bring Fam10 memory controller init up to date with the latest AMD BKDG by Marc Jones (marc.jones · 16 years ago
  94. f8ee180 Rename almost all occurences of LinuxBIOS to coreboot. by Stefan Reinauer · 16 years ago
  95. 7e61e45 Please bear with me - another rename checkin. This qualifies as trivial, no by Stefan Reinauer · 16 years ago
  96. 8ae8c88 Initial AMD Barcelona support for rev Bx. by Marc Jones · 16 years ago