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review.coreboot.org / coreboot / a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 / src / soc / intel / baytrail / pcie.c
  1. a342f39 src: Remove unneeded whitespace by Elyes HAOUAS · 6 years ago
  2. 17a3ceb soc/intel/baytrail: Get rid of device_t by Elyes HAOUAS · 6 years ago
  3. 4a83f1c src/soc: Add required space before opening parenthesis '(' by Elyes HAOUAS · 8 years ago
  4. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  5. 580e722 devicetree: Change scan_bus() prototype in device ops by Kyösti Mälkki · 9 years ago
  6. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  7. 5c8d43e baytrail: fix the coding error on PCIe L1 exit latency by Kevin L Lee · 10 years ago
  8. d946f5e Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms by Kevin Hsieh · 10 years ago
  9. 18ea2d3 baytrail: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  10. 97acc5e Baytrail: Fix no_dev_behind_port not executed for RP1/2/3. by Kenji Chen · 10 years ago
  11. e237f5a Baytrail: Change PCIe root disable algorithm by Kenji Chen · 10 years ago
  12. 99a3bba intel/baytrail: Spelling fixes by Martin Roth · 10 years ago
  13. 3511023 baytrail/rambi: S3 support and other updates by Kein Yuan · 10 years ago
  14. 616f394 baytrail: utilize reg_script_run_on_dev() by Aaron Durbin · 11 years ago
  15. ae31f7d baytrail: pcie: Root port initialization by Aaron Durbin · 11 years ago