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review.coreboot.org / coreboot / a247d8e53cebbd754e46f76412ed9d17df752308 / src / soc / intel / apollolake / chip.h
  1. a247d8e soc/intel/apollolake: Set PL1 limits for RAPL MSR registers by Sumeet Pawnikar · 8 years ago
  2. ef8deaf soc/intel/apollolake: Add PM methods to power gate PCIe by Vaibhav Shankar · 8 years ago
  3. 88df48c soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cb by Venkateswarlu Vinjamuri · 8 years ago
  4. 41a3fa6 soc/intel/apollolake: add option for SLP_S3_L assertion width by Aaron Durbin · 8 years ago
  5. 6e37e90 soc/intel/apollolake: Include gpe.h in chip.h by Furquan Shaikh · 8 years ago
  6. cd9e1e4 intel/apollolake: Update gnvs for dptf by Shaunak Saha · 8 years ago
  7. 89e7b49 soc/intel/apollolake: Consolidate ISH enabling by Andrey Petrov · 8 years ago
  8. d9fc5fb soc/intel/apollolake: Include gpio_defs header by Harsha Priya · 8 years ago
  9. e46dbcc soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree by Saurabh Satija · 8 years ago
  10. 5b6c5a5 soc/intel/apollolake: Add GPE routing code by Shaunak Saha · 8 years ago
  11. ff8bce0 soc/intel/apollolake: Add support for LPSS I2C driver by Duncan Laurie · 8 years ago
  12. 1b8ee0b soc/intel/apollolake: Add EMMC DLL API by Zhao, Lijian · 8 years ago
  13. 483004f soc/apollolake: Add ish_enable in soc_intel_apollolake_config by Hannah Williams · 8 years ago
  14. 3aa34a8 soc/apollolake/lpc: Allow configuring SERIRQ via devicetree by Alexandru Gagniuc · 8 years ago
  15. c1526f0 Revert "soc/intel/apollolake: Enable LPC bus interface" by Alexandru Gagniuc · 8 years ago
  16. e976bd4 soc/intel/apollolake: Enable LPC bus interface by Andrey Petrov · 8 years ago
  17. ebabfad soc/intel: Update license headers by Martin Roth · 8 years ago
  18. 70efecd soc/intel/apollolake: Add chip initialization by Andrey Petrov · 8 years ago