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review.coreboot.org / coreboot / 9ede2ffee845d243d8e1515effbc206152fbc7fd / src / northbridge / intel / pineview / memmap.c
  1. f091f4d intel/smm/gen1: Rename header file by Kyösti Mälkki · 5 years ago
  2. 544878b arch/x86: Add postcar_frame_common_mtrrs() by Kyösti Mälkki · 5 years ago
  3. 5bc641a cpu/intel: Refactor platform_enter_postcar() by Kyösti Mälkki · 5 years ago
  4. fe481eb northbridge/intel: Rename ram_calc.c to memmap.c by Kyösti Mälkki · 5 years ago[Renamed from src/northbridge/intel/pineview/ram_calc.c]
  5. bccd2b6 intel/i945,gm45,pineview,x4x: Fix stage cache location by Kyösti Mälkki · 5 years ago
  6. aba8fb1 intel/i945,gm45,pineview,x4x: Move stage cache support function by Kyösti Mälkki · 5 years ago
  7. 6e2d0c1 arch/x86: Adjust size of postcar stack by Kyösti Mälkki · 5 years ago
  8. 065857e arch/io.h: Drop unnecessary include by Kyösti Mälkki · 5 years ago
  9. f1b58b7 device/pci: Fix PCI accessor headers by Kyösti Mälkki · 5 years ago
  10. de6bda6 nb/intel/pineview: Use common code for SMM in TSEG by Arthur Heymans · 6 years ago
  11. 64f6b71 src/northbridge: Fix typo by Elyes HAOUAS · 6 years ago
  12. aa7cf55 nb/intel/pineview: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  13. 089b908 nb/intel: Use postcar_frame_add_romcache() by Nico Huber · 6 years ago
  14. 654cc2f {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate by Nico Huber · 6 years ago
  15. 62e784b nb/intel/pineview: Move to early cbmem by Arthur Heymans · 7 years ago
  16. f564606 nb/intel/pineview: Fix decode_pciebar() by Damien Zammit · 9 years ago
  17. f7060f1 northbridge/intel/pineview: Add remaining boilerplate code for northbridge by Damien Zammit · 9 years ago
  18. 6247793 northbridge/intel/pineview: Add minimal Pineview northbridge by Damien Zammit · 9 years ago