Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 9ed54f99c7e86b49cc4d3207a98d56be994cda23 / src / soc / rockchip / rk3288 / sdram.c
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 8 years ago
  2. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 8 years ago
  3. ed84a8f rockchip/rk3288: Fix operator precedence error in LPDDR init by Julius Werner · 8 years ago
  4. 9418476 arm(64): Manually clean up the mess left by write32() transition by Julius Werner · 9 years ago
  5. 2f37bd6 arm(64): Globally replace writel(v, a) with write32(a, v) by Julius Werner · 9 years ago
  6. 5c8aacf rockchip: configure lpddr odt properly by Derek Basehore · 9 years ago
  7. 8cc3a2a rk3288: support single channel ddr by jinkun.hong · 9 years ago
  8. ee28c86 rk3288: detect sdram size at runtime by huang lin · 9 years ago
  9. 129b5fa rk3288: Fix failing LPDDR3 reboot test by jinkun.hong · 9 years ago
  10. d4a227b rk3288: Fix failing DDR3 reboot test by jinkun.hong · 9 years ago
  11. 8188ab7 rk3288: Increase the delay after DDR reset de-assert to 10us. by Dailunxue · 9 years ago
  12. 7a453eb rk3288: Change all SoC headers to <soc/headername.h> system by Julius Werner · 9 years ago
  13. b6092b7 veyron_pinky/rk3288: Use KHz, MHz and GHz constants by Julius Werner · 9 years ago
  14. 3e9ea16 coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz by jinkun.hong · 9 years ago
  15. 82ba4d0 rk3288: add cpu and chip by huang lin · 9 years ago
  16. c33ce35 rk3288: add ddr driver by Jinkun Hong · 9 years ago