Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 9b1c7c16451fc8bf12a20fe61a645b14216b3229
  1. 9b1c7c1 coreinfo: Fix the subwindow refresh based on the libpayload changes by Jordan Crouse · 16 years ago
  2. 9dac1b4 libpayload: Add an exec() and i386_do_exec() function by Jordan Crouse · 16 years ago
  3. 5069808 libpayload: Add larfptr function by Jordan Crouse · 16 years ago
  4. d43841d libpayload: Fix curses subwindows by Jordan Crouse · 16 years ago
  5. 9d10dc4 Add post-RAM init code for the Fintek F71805F Super I/O. by Corey Osgood · 16 years ago
  6. fcb2a31 Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R. by Aaron Lwe · 16 years ago
  7. 710e8b1 Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial). by Uwe Hermann · 16 years ago
  8. ce1fb9d flashrom: Support Pm49FL004/2 Block Locking Registers by Nikolay Petukhov · 16 years ago
  9. fb047a6 I looked at the datasheet and erase_sector_39sf020() is totally and by Carl-Daniel Hailfinger · 16 years ago
  10. 85e46e6 Doesn't have to be executable (trivial). by Uwe Hermann · 16 years ago
  11. 2ee5c9e Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all by Marc Jones · 16 years ago
  12. 0fd8ccd New Target and initial support for the Thomson IP1000. by Joseph Smith · 16 years ago
  13. d9fa5d2 ICH8 and ICH9 have an almost identical SPI interface, only the location by Carl-Daniel Hailfinger · 16 years ago
  14. ed24da4 Add support for the Atmel AT25DF321 SPI flash (tested). by Dominik Geyer · 16 years ago
  15. fac0afb Add support for SPI chips on ICH9. This is done by using the generic SPI by Dominik Geyer · 16 years ago
  16. e7b1157 Enable IT8716F LPC-to-SPI write cycle translation in flashrom if the by Carl-Daniel Hailfinger · 16 years ago
  17. 8e8eb7d Print detailed status register information for SST25VF series flash. by Carl-Daniel Hailfinger · 16 years ago
  18. da69582 This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge. by Joseph Smith · 16 years ago
  19. e3da00d Lots of new SST flash chip IDs. Only a subset has been added to by Carl-Daniel Hailfinger · 16 years ago
  20. a4868c4 Add support for the JEDEC RES (Read Electronic Signature and Resume from by Carl-Daniel Hailfinger · 16 years ago
  21. c7d29013 Some NSC Super I/Os can have their config port at 0x15c (trivial). by Uwe Hermann · 16 years ago
  22. 9a6b6b5 Cosmetics, whitespace, coding style, partially ident-aided (trivial). by Uwe Hermann · 16 years ago
  23. 621c095 libpayload: implement wborder function by Jordan Crouse · 16 years ago
  24. 3148935 libpayload: Fix the putc function by Jordan Crouse · 16 years ago
  25. f9b9945 add ICH7-M and ICH7 DH to inteltool (trivial) by Stefan Reinauer · 16 years ago
  26. 3f09561 Add more infrastructure for flashrom ICH9 support. by Carl-Daniel Hailfinger · 16 years ago
  27. 58a1cc1 fix license mentioning in manpage (trivial) by Stefan Reinauer · 16 years ago
  28. 9f7af6e trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge by Stefan Reinauer · 16 years ago
  29. d466e6a trivial patch to fix options. Thanks to Uwe Hermann for the hint! by Stefan Reinauer · 16 years ago
  30. e173f99 Add the Intel 6300ESB as known chipset to the chipset struct enables. by Claus Gindhart · 16 years ago
  31. 42aab08 Fix crash caused by division by zero for unknown flash chips. by Carl-Daniel Hailfinger · 16 years ago
  32. 68db3a2 Check the JEDEC vendor ID for correct parity. Flash chips which can be by Carl-Daniel Hailfinger · 16 years ago
  33. b69e46b Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7 by Stefan Reinauer · 16 years ago
  34. 1984067 Add lots of ATMEL SPI flash chips to flash.h. by Carl-Daniel Hailfinger · 16 years ago
  35. b77fb6b flashrom: Move all IT87xx specific SPI routines from spi.c to a separate by Carl-Daniel Hailfinger · 16 years ago
  36. 03646be Add new revised inteltool that dumps all kinds of chipset information and drop old by Stefan Reinauer · 16 years ago
  37. 56cc34a This is a trivial patch which fixes the tint build by removing the extra by Myles Watson · 16 years ago
  38. 967214d flashrom: Move the SPI #defines from spi.c to spi.h by Carl-Daniel Hailfinger · 16 years ago
  39. a2e7c48 Change the SPI parts of flashrom to prepare for a merge of by Carl-Daniel Hailfinger · 16 years ago
  40. 6d3fdf9 MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OK by Carl-Daniel Hailfinger · 16 years ago
  41. c95f2a7 Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF by Carl-Daniel Hailfinger · 16 years ago
  42. d0e687a Fix the build when serial console support is disabled (trivial). by Uwe Hermann · 16 years ago
  43. 134aaae Quickfix to repair 'make clean; make menuconfig' (trivial). by Uwe Hermann · 16 years ago
  44. cd0b563 Improve flashrom SPI abstraction, second step. by Carl-Daniel Hailfinger · 16 years ago
  45. 31ab031 flashrom: Rename generic_spi_*() functions to spi_*() by Peter Stuge · 16 years ago
  46. fa36f50 coreboot-v2: Disable second serial port on Norwich by Jordan Crouse · 16 years ago
  47. bbd337e Add support for dumping ITE IT8718F EC registers (trivial). by Uwe Hermann · 16 years ago
  48. 8cb2458 Don't split up register list in two blocks, otherwise "Register dump:" by Uwe Hermann · 16 years ago
  49. 15da8ed flashrom: Probe for up to 3 flash chips. by Claus Gindhart · 16 years ago
  50. 83a965d Implement GPIO configuration routines for the Intel 3100 southbridge, by Ed Swierk · 16 years ago
  51. aa6e378 coreinfo: Add a module for browsing the boot LAR by Jordan Crouse · 16 years ago
  52. 681ec27 libpayload: Add LAR walking support by Jordan Crouse · 16 years ago
  53. 35993a2 Fix a typo in lbtdump output (trivial). by Ed Swierk · 16 years ago
  54. 1933786 coreinfo: Show the current time and date in the menu by Jordan Crouse · 16 years ago
  55. de7fc55 We were in the risk of running out of space in the option menu at by Jordan Crouse · 16 years ago
  56. 7ce2666 The previous commit had more in it then I wanted - so I am reverting by Jordan Crouse · 16 years ago
  57. 646ee3e coreinfo: Move the rdtsc.h include into the #ifdef CONFIG_MODULE_CPUINFO by Jordan Crouse · 16 years ago
  58. 9d9518f cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a by Marc Jones · 16 years ago
  59. c314b2f This patch changes Config-lab.lb for qemu to use lzma like the other targets. by Myles Watson · 16 years ago
  60. 2342f8b This patch adds pc keyboard init function call for qemu in v2 since some payloads assume by Aaron Lwe · 16 years ago
  61. 4f91417 Fix various issues on MSI MS-7135 board. by Jonathan A. Kollasch · 16 years ago
  62. 33c57f8 by Ward Vandewege · 16 years ago
  63. 4934fc0 flashrom: Add a tested bitmap field to the flash chip table. by Peter Stuge · 16 years ago
  64. a9a5f49 By default, the Intel 3100 LPC interface enables only I/O range 0x3f8 by Ed Swierk · 16 years ago
  65. e21f836 flashrom: Enable ROM decode range to 1MB for vt8237r by Bari Ari · 16 years ago
  66. b19973e The generic jedec.c does not work for the ST M50FLW flash by Claus Gindhart · 16 years ago
  67. 26e08b5 flashrom: Handle NULL probe, erase and write function pointers in the by Peter Stuge · 16 years ago
  68. e227143 libpayload: Add gettimeofday() and friends by Jordan Crouse · 16 years ago
  69. d772e1e libpayload: Fix a small but aggressive bug in printf() by Jordan Crouse · 16 years ago
  70. 63f181f libpayload: Enable keyboard translation so that we can use scancode set 1 by Jordan Crouse · 16 years ago
  71. 24a0404 libpayload: Fix malloc allocation by Jordan Crouse · 16 years ago
  72. c781584 libpayload: Add the null terminator to the end of the duplicated string by Jordan Crouse · 16 years ago
  73. 20ce60c Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb. by Marc Jones · 16 years ago
  74. 65e0804 Remove inline from FAM10 CPU initialization functions. by Marc Jones · 16 years ago
  75. 7ca3ec2 Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC. by Aaron Lwe · 16 years ago
  76. 6fd385d Payload location fix for buildrom (trivial). by Uwe Hermann · 16 years ago
  77. c1cbff2 Add CPUID processor name string support for Fam10 CPUs. by Marc Jones · 16 years ago
  78. 403b89a On APs the ClLinesToNbDis was being left enabled from CAR setup. by Marc Jones · 16 years ago
  79. 202625e This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX) by Nikolay Petukhov · 16 years ago
  80. 20ba8eb Flash pages, which where excluded from updating using the exclude or the by Claus Gindhart · 16 years ago
  81. a149131 Same old story: Fam10 needs more space again. My calculations say it by Carl-Daniel Hailfinger · 16 years ago
  82. e3e4981 Trivial payload location changes for buildrom. by Myles Watson · 16 years ago
  83. e4c98d2 These config files are so that buildrom can use these two boards. by Myles Watson · 16 years ago
  84. 3d1d3b2 by Myles Watson · 16 years ago
  85. 0eec1a8 by Myles Watson · 16 years ago
  86. bb33e4a Detect SMSC SCH5027 (trivial). by Uwe Hermann · 16 years ago
  87. c4a4116 by Ward Vandewege · 16 years ago
  88. a74a8ff Clean up and remove late initialization code that is no longer needed. by Marc Jones · 16 years ago
  89. f0174b5 Find matching settings for each CPUs FID, VID, and P-state registers and initialize them. by Marc Jones · 16 years ago
  90. 8127dc4 Update the FAM10 microcode to current versions. by Marc Jones · 16 years ago
  91. c74e362 Missed this file in the previous check-in, r3248. by Marc Jones · 16 years ago
  92. da4ce6b Add early MSR and PCI register initialization. by Marc Jones · 16 years ago
  93. 0ab8cdd Add support for a 'bootlog' module to coreinfo. by Uwe Hermann · 16 years ago
  94. 16acf8b Show index numbers in the NVRAM dump, similar to the PCI config space dump. by Uwe Hermann · 16 years ago
  95. 5f4410b libpayload: Fix keyboard buglet by Jordan Crouse · 16 years ago
  96. 7bc63fd This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the by Christopher Kilgour · 16 years ago
  97. 5971121 Replace buildtarget's check for --build-id with something by Ed Swierk · 16 years ago
  98. 68aab26 Alter buildtarget to invoke the cross-compiler when by Ed Swierk · 16 years ago
  99. 8d0a12a Change default payload location for easier buildrom support (trivial). by Uwe Hermann · 16 years ago
  100. 0b53ec3d Move curses/speaker.c to drivers/ as it's not curses-specific (trivial). by Uwe Hermann · 16 years ago