- 98fcc09 Add AMD SR56x0 support. by Zheng Bao · 13 years ago
- 8a28188 This is for board Supermicro H8scm. The code was done by existing chips and by Zheng Bao · 13 years ago
- 0446f96 X60: Add notification for LID objects by Sven Schnelle · 13 years ago
- e106999 X60: remove beep call from _Q26/_Q27 by Sven Schnelle · 13 years ago
- 4a46e89 Fix breaking the build after removing files in tthe previous checkin. by Marc Jones · 13 years ago
- 9c2fb60 Perform cleanup and file shrinkage of the AMD AGESA code. by Frank.Vibrans · 13 years ago
- ea1c0a7 Fix power_on_after_fail handling on AMD SB600 by Josef Kellermann · 13 years ago
- 0882728 X60: Clear EC events when wake GPE is triggered by Sven Schnelle · 13 years ago
- f9a0b92 ACPI EC: add ec_query function by Sven Schnelle · 13 years ago
- 07ca1c4 X60: LPC bus is LPCB, not LPC by Sven Schnelle · 13 years ago
- 91c31da X60: fix typo in dsdt.asl by Sven Schnelle · 13 years ago
- b188a93 X60: Add _PRW/_PSW methods to LID/SLPB objects by Sven Schnelle · 13 years ago
- 0238a9c ec/acpi: make ACPI register pair configurable by Sven Schnelle · 13 years ago
- 8d94d7c ACPI EC: add ec_set_bit() / ec_clr_bit() by Sven Schnelle · 13 years ago
- 314dd0b Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. by Scott Duplichan · 13 years ago
- 57205c7 Add option_table.h as dependency for all C based object files if option tables are used. by Patrick Georgi · 13 years ago
- fab35e3 Move cmos.default handling to bootblock by Patrick Georgi · 13 years ago
- 85e666d X60: add thermal zone 1 by Sven Schnelle · 13 years ago
- b641e98 X60: add thermal zone 0 by Sven Schnelle · 13 years ago
- 09b3629 Add P-states for select Socket 754 processors. by Jonathan Kollasch · 13 years ago
- c9a08dd Redo r6099 after copy&pasted code reintroduced DIMMx #defines by Patrick Georgi · 13 years ago
- d5782f3 Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code. by Jonathan Kollasch · 13 years ago
- fadb004 Improve ck804 IOAPIC and HPET resource handling. by Jonathan Kollasch · 13 years ago
- a73ffa0 Configure PCIe lanes on ms7135 as original BIOS does. by jakllsch · 13 years ago
- 071d835 add PC87384 SuperIO by Sven Schnelle · 13 years ago
- 7b9bbee Fixes licensing of src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3. by Alexandru Gagniuc · 13 years ago
- 8241941 Fix some subsystemid statements in r6421 by Sylvain "ythier" Hitier · 13 years ago
- b8269e2 Fix a simple whitespace error in src/include/device/device.h by Sven Schnelle · 13 years ago
- 9132102 Use subsystem id from devicetree.cb instead of Kconfig and move by Sven Schnelle · 13 years ago
- 270a908 Add subsystemid option to sconfig by Sven Schnelle · 13 years ago
- 11ac1cf Mark non-returning function as noreturn to help some compiler versions by Patrick Georgi · 13 years ago
- d175f44 add functions to set Subsystem Vendor/Device to rl5c746 by Sven Schnelle · 13 years ago
- b671172 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 6bdc83b Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 061c89e Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- c313210 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 6276b6f Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 82b241a Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 5bcedee Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- ce62350 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- e80ce0a Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 26f97d2 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 19245c9 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 9cbcf1a Kino devicetree.cb SIO PNP devices were not matched up with the by Marc Jones · 13 years ago
- e485aa4 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 6fcc961 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 1f93fea Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 0e5d3e1 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- adb23a5 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 1f4fffb Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- f7ef421 Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- d26e5e6 Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 40f9b4b0 Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 1d80e51 Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 9683b1d Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- a5cbd25 Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- d729459 Prepare for next patches (Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- 70a3733 Add 300 MHz and 500 MHz HT frequency limits by Xavi Drudis Ferran · 13 years ago
- 4c28a6f Make AMD Fam10h CPU microcode updates optional in Expert mode by Xavi Drudis Ferran · 13 years ago
- 837403d Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8,GPM9 as reset toggles. by Rudolf Marek · 13 years ago
- 656060d Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh. by Scott Duplichan · 13 years ago
- 63896e7 Add support for the ASRock E350M1, an AMD family 14h Fusion board. by Scott Duplichan · 13 years ago
- 199c694 It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. by Rudolf Marek · 13 years ago
- ed1d116 Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS by Josef Kellermann · 13 years ago
- 855224b Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600 by Josef Kellermann · 13 years ago
- 20bd196 Tyan/s2735 doesn't need to define its own hard_reset function anymore. by Patrick Georgi · 13 years ago
- a649a96 by Scott Duplichan · 13 years ago
- 541269b [i945] Add SPD adress mapping by Sven Schnelle · 13 years ago
- 0c8e664 It turns out that the code which enables specific LDN is somewhat buggy. by Rudolf Marek · 14 years ago
- 650cf23 Fix build errors introduced in r6367 by Alexandru Gagniuc · 14 years ago
- e8a7df8 Add ACPI code for Lenvo X60 by Sven Schnelle · 14 years ago
- 025ead7 Extended K8T890 driver to include the K8T800 and K8M800 northbridges by Alexandru Gagniuc · 14 years ago
- ddb3f0a Lenovo ThinkPad X60: Enable SMI handler by Sven Schnelle · 14 years ago
- 7afbb99 Remove more files and lines mistakenly copied from Roda to X60 by Peter Stuge · 14 years ago
- 7d5966d Remove ACPI mistakenly copied from Roda to ThinkPad X60 by Peter Stuge · 14 years ago
- 1c427a7 Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be addded by the developer if needed. by Marc Jones · 14 years ago
- dd6c1e6 SERIAL_POST was renamed to CONSOLE_POST a while ago by Stefan Reinauer · 14 years ago
- e2ca71e Lenovo ThinkPad X60 / X60s Support by Sven Schnelle · 14 years ago
- f0ccf6e Errata #169 works on HT, not MC by Josef Kellermann · 14 years ago
- cf37a59 Removed LPC DMA Deadlock workaround... by Josef Kellermann · 14 years ago
- 144fe88 Fix Typo. (and why is that file, and some of its siblings per-board?) by Patrick Georgi · 14 years ago
- 69da1b6 Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. by Frank Vibrans · 14 years ago
- 7b904d8 This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code. by Frank Vibrans · 14 years ago
- 6b4674e I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347. by Frank Vibrans · 14 years ago
- d0a8ebf This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD code. by Frank Vibrans · 14 years ago
- 0822ad8 This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code. by Frank Vibrans · 14 years ago
- 420faca Add AMD cpu wrapper code. Patch 4 of 8. by Frank Vibrans · 14 years ago
- 63e62b0 This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code. by Frank Vibrans · 14 years ago
- 39fca80 This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code. by Frank Vibrans · 14 years ago
- 2b4c831 Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8. by Frank Vibrans · 14 years ago
- 74ad66c Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC. by Rudolf Marek · 14 years ago
- daecb18 According to AMD documentation, cache type WP should be used for by Scott Duplichan · 14 years ago
- 20ecc5a RS690: Provide support for MMCONF. by Josef Kellermannseppk · 14 years ago
- 1df8542 Implemented workaround for erratum 169, obsoleting erratum 131. by Alexandru Gagniuc · 14 years ago
- 31e0deac0 Fix a potential system hang by handling AMD Model F Erratum 89 a bit later. by Josef Kellermann · 14 years ago
- 4a038ca Place the W83627EHG MIDI base address mask in the correct position. by Alexandru Gagniuc · 14 years ago
- b1d1c4d Reliably build arbitrary Kconfig-based revisions of SeaBIOS by Peter Stuge · 14 years ago
- 1440d08 Actually add PC87382 into Kconfig, missing from r6332 by Peter Stuge · 14 years ago
- 82e3617 Add PC87392 support by Sven Schnelle · 14 years ago
- 92cf08c Add PC87382 support by Sven Schnelle · 14 years ago