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review.coreboot.org / coreboot / 98adaf5989845f7859054f5cee2cf1f4e0392640 / src / northbridge / intel / x4x / raminit_ddr2.c
  1. ef7e98a nb/intel/x4x: Implement resume from S3 suspend by Arthur Heymans · 8 years ago
  2. 97e13d8 nb/intel/x4x: Fix raminit on reset path by Arthur Heymans · 8 years ago
  3. eee4f6b nb/x4x/raminit: Fix programming dram timings by Arthur Heymans · 8 years ago
  4. 128c104 nb/intel: Fix some spelling mistakes in comments and strings by Martin Roth · 8 years ago
  5. 8a3514d nb/x4x/raminit.c: Improve crossclock table cosmetics by Arthur Heymans · 8 years ago
  6. 523e90f nb/intel/x4x: Increase MMIO PCI space to 2GiB by Damien Zammit · 8 years ago
  7. 12df950 northbridge/intel: Add required space before opening parenthesis '(' by Elyes HAOUAS · 8 years ago
  8. 27f94ee x4x: add non documented vram sizes by Arthur Heymans · 8 years ago
  9. 7c2e539 nb/intel/x4x: Fix CAS latency detection and max memory detection by Damien Zammit · 8 years ago
  10. 68e1dcf nb/intel/x4x: Fix unpopulated value by Damien Zammit · 8 years ago
  11. d63115d nb/intel/x4x: Tidy up raminit and fix msbpos() function by Damien Zammit · 9 years ago
  12. 9fb08f5 nb/intel/x4x: Fix memory hole with both channels populated by Damien Zammit · 9 years ago
  13. cbe3892 northbridge/intel/x4x: clean up includes by Martin Roth · 9 years ago
  14. 4b513a6 northbridge/intel/x4x: Native raminit by Damien Zammit · 9 years ago