- a5c49b8 arch/riscv: Update encoding.h and adjust related code by Jonathan Neuschäfer · 4 years, 5 months ago
- c0c31b6 riscv: Remove config string support by Jonathan Neuschäfer · 4 years, 7 months ago
- 3ca8b59 arch/riscv: Remove the current SBI implementation by Jonathan Neuschäfer · 4 years, 7 months ago
- b0de851 arch/riscv: Return from trap_handler instead of jumping out by Jonathan Neuschäfer · 4 years, 7 months ago
- 3f75f5d arch/riscv: Unify trap return by Jonathan Neuschäfer · 4 years, 7 months ago
- c90f1d7 arch/riscv: gettimer: Don't use the config string by Jonathan Neuschäfer · 4 years, 9 months ago
- 5a01d6a arch/riscv: trap handler: Print load/store access width in bits by Jonathan Neuschäfer · 4 years, 9 months ago
- e18e642 src: change coreboot to lowercase by Martin Roth · 5 years ago
- c5ebb1d riscv: Move mcall numbers to mcall.h, adjust their names by Jonathan Neuschäfer · 5 years ago
- 6f3a53b riscv: get SBI calls to work by Ronald G. Minnich · 5 years ago
- d9307c2 riscv: Add support for timer interrupts by Ronald G. Minnich · 6 years ago
- 99f2f11 riscv: Unify SBI call implementations under arch/riscv/ by Jonathan Neuschäfer · 6 years ago
- 571c230 riscv: Add a bandaid for the new toolchain by Ronald G. Minnich · 6 years ago
- 0bc12ab arch/riscv: In trap handler, don't print SP twice by Jonathan Neuschäfer · 6 years ago 4.5
- 2f72a61 arch/riscv: Visually align trap frame information by Jonathan Neuschäfer · 6 years ago
- 2af174a riscv and power8: Convert printk/while(1) to die by Jonathan Neuschäfer · 6 years ago
- a1e3924 arch/riscv: Add missing "break;" by Jonathan Neuschäfer · 6 years ago
- 857e33e arch/riscv: Implement the SBI again by Jonathan Neuschäfer · 6 years ago
- b6648cd arch/riscv: Fix unaligned memory access emulation by Jonathan Neuschäfer · 6 years ago
- 363526c arch/riscv: Improve and refactor trap handling diagnostics by Jonathan Neuschäfer · 6 years ago
- 1b1d4b7 arch/riscv: Enable unaligned load handling by Jonathan Neuschäfer · 6 years ago
- fefc77a arch/riscv: Show fault PC and load address on load access faults by Jonathan Neuschäfer · 6 years ago
- 38cd375 RISC-V: Add more debug info to debug printks by Andrew Waterman · 6 years ago
- f16d904 RISC-V: Make inline asm usage safer by Andrew Waterman · 6 years ago
- a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 7 years ago
- d9653e1 riscv-trap-handling: Add functionality, prevent stack corruption by Thaminda Edirisooriya · 7 years ago
- 95ba4c8 riscv-trap-handling: Add implementation for trap calls in riscv by Thaminda Edirisooriya · 7 years ago