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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / northbridge / amd / amdmct / mct_ddr3
  1. 5edc669 nb/amd/mct_ddr3: Add Family 15h tristate enable codes by Timothy Pearson · 9 years ago
  2. 3093038 nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time by Timothy Pearson · 9 years ago
  3. 01b9f8e nb/amd/mct_ddr3: Use antiphase to better center DQS window by Timothy Pearson · 9 years ago
  4. 4502df1 nb/amd/mct_ddr3: Fix odd rank data corruption by Timothy Pearson · 9 years ago
  5. df499b5 nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select error by Timothy Pearson · 9 years ago
  6. 0eb163d nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set by Timothy Pearson · 9 years ago
  7. ab1e77f northbridge/amd/amdmct/mct_ddr3: Add CC6 setup information messages by Timothy Pearson · 9 years ago
  8. c8e1073 northbridge/amd/amdmct/mct_ddr3: Add DDR3 termination debug output by Timothy Pearson · 9 years ago
  9. 68130f5 amd/amdfam10: Control Fam15h cache partitioning via nvram by Timothy Pearson · 9 years ago
  10. 845b00c amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs by Timothy Pearson · 9 years ago
  11. 0d2fdeb amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance by Timothy Pearson · 9 years ago
  12. eb295a3 nb/amd/amdmct/mct_ddr3: Force DRAM retraining on every boot by Timothy Pearson · 9 years ago
  13. 4530df4 northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file by Timothy Pearson · 9 years ago
  14. 0122afb cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence by Timothy Pearson · 9 years ago
  15. 29016ea northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h by Timothy Pearson · 9 years ago
  16. f682d00 amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h by Timothy Pearson · 9 years ago
  17. dc4cb05 nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots by Timothy Pearson · 9 years ago
  18. a44daac northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure by Timothy Pearson · 9 years ago
  19. 4ef4fc6 northbridge/amd/amdmct/mct_ddr3: Properly indicate clobbered registers by Timothy Pearson · 9 years ago
  20. dee6b1f northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in use by Timothy Pearson · 9 years ago
  21. f3aa375 northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values by Timothy Pearson · 9 years ago
  22. b7a8b8c northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs by Timothy Pearson · 9 years ago
  23. 11739a4 northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue by Timothy Pearson · 9 years ago
  24. 9426e4f northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors by Timothy Pearson · 9 years ago
  25. 5288ced amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values by Timothy Pearson · 9 years ago
  26. 38508a0 cpu/amd: Fix AMD Family 15h ECC initialization reliability issues by Timothy Pearson · 9 years ago
  27. eb2f6ff northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init by Timothy Pearson · 9 years ago
  28. 0d0375b northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements by Timothy Pearson · 9 years ago
  29. 0e545c6 northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables by Timothy Pearson · 9 years ago
  30. 31ec0f3 northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration by Timothy Pearson · 9 years ago
  31. 7fd3ef5 northbridge/amd/amdmct: Clear memory before enabling ECC by Timothy Pearson · 9 years ago
  32. f3b9fd3 src/northbridge/amd/amdmct: Add option to override bad SPD checksum by Timothy Pearson · 9 years ago
  33. f70946f northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training by Timothy Pearson · 9 years ago
  34. 45de61d northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged by Timothy Pearson · 9 years ago
  35. 83abd81 cpu/amd: Add CC6 support by Timothy Pearson · 9 years ago
  36. 74e03a4 mainboard/asus/kgpe-d16: Enable CC6 by Timothy Pearson · 9 years ago
  37. cfb93e7 northbridge/amd/amdfam10: Enable CC6 DRAM save area setup by Timothy Pearson · 9 years ago
  38. df1fb9c amd/amdmct/mct_ddr3: Use training values from previous boot if possible by Timothy Pearson · 9 years ago
  39. 45ded7d amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability by Timothy Pearson · 9 years ago
  40. 69ded8f northbridge/amd/amdmct/mct_ddr3: Clean up curly brace style violations by Timothy Pearson · 9 years ago
  41. 453b543 northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time by Timothy Pearson · 9 years ago
  42. 6ee6bde amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h by Timothy Pearson · 9 years ago
  43. 730a043 cpu/amd: Add initial AMD Family 15h support by Timothy Pearson · 9 years ago
  44. 69b11f9 northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend overrunning the stack size limit by Timothy Pearson · 9 years ago
  45. 2a83935 northbridge/amd/amdfam10: Set DIMM voltage based on SPD data by Timothy Pearson · 9 years ago
  46. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  47. 59d0e04 northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) support by Timothy Pearson · 9 years ago
  48. b8a355d northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization by Timothy Pearson · 9 years ago
  49. a8d73a3 northbridge/amd/amdmct: Fix Family 15h detection by Timothy Pearson · 9 years ago
  50. 76d4636 northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violations by Timothy Pearson · 9 years ago
  51. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  52. 620fa5f northbridge/amd/amdfam10: Collect DIMM information for ramstage use by Timothy Pearson · 9 years ago
  53. d5c82af northbridge/amd/amdmct: Pack MCT and DCT info structs by Timothy Pearson · 9 years ago
  54. 2012b81 northbridge/amd/amdmct: Fix FTBFS with node interleaving enabled by Timothy Pearson · 10 years ago
  55. f4cb412 northbridge/amd: Doxygen fixes by Martin Roth · 10 years ago
  56. 65b72ab northbridge: Drop print_ implementation from non-romcc boards by Stefan Reinauer · 10 years ago
  57. 0f92f63 Uniformly spell frequency unit symbol as Hz by Elyes HAOUAS · 10 years ago
  58. ba363d3 northbridge/amd/amdmct: Superfluous parenthesis in if-statements by Edward O'Callaghan · 10 years ago
  59. 72ae4a3 northbridge/amd/amdmct/mct: Initialize variables at the eol by Edward O'Callaghan · 10 years ago
  60. 029aaf6 x86: add common definitions for control registers by Aaron Durbin · 11 years ago
  61. 42409e8 northbridge/amd/amdmct: Use `static const` instead of `const static` by Paul Menzel · 11 years ago
  62. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  63. 067d223 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. by Marc Jones · 12 years ago
  64. 328a694 AMD CPU and chipset fixes for compilation with gcc 4.6 by Stefan Reinauer · 13 years ago
  65. 471f103 This patch sets max freq defaults for ddr2 and ddr3for fam10. by Marc Jones · 13 years ago
  66. dd676dd For Cx, each ChipSel need to be sent MR command. by Zheng Bao · 14 years ago
  67. a7296e7 The code is tested on my board with register DIMMs. More tests need to be by Zheng Bao · 14 years ago
  68. 69436e1 Fix some settings fo AMD MCT. It is based on BIOS test suite. by Zheng Bao · 14 years ago
  69. ea62e9b More explicite and straight way to set seed. by Zheng Bao · 14 years ago
  70. 8912285 Trivial. Clean up code and add some comments. by Zheng Bao · 14 years ago
  71. 53b52f3 Trivial. Spell checking. by Zheng Bao · 14 years ago
  72. 1dcf6689 Trivial. Spell checking. by Zheng Bao · 14 years ago
  73. c3af12f Trivial. Spell checking. by Zheng Bao · 14 years ago
  74. 3d682fe Trivial. Fix the typo. by Zheng Bao · 14 years ago
  75. 52000e1 Trivial. Re-indent the code. by Zheng Bao · 14 years ago
  76. 7b1a3c3 Trivial. re-Indent the code. by Zheng Bao · 14 years ago
  77. 7cdf1ec Obviously missing brackets. by Xavi Drudis Ferran · 14 years ago
  78. 951a0fe Fix the typo. Field DisAutoRefresh is in DramTimngHi. by Zheng Bao · 14 years ago
  79. e150e9a Also improve boot time on AMD for the DDR3 code path. Fix a typo, too. by Arne Georg Gleditsch · 14 years ago
  80. f7a999a Trivial. Currently the max frequency is preset as 400Mhz. We need to set a by Zheng Bao · 14 years ago
  81. 08c92e0 AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. by Kerry She · 14 years ago
  82. 9fae99f Get Byte65/66 for register manufacture ID code. RegMan1Present will by Zheng Bao · 14 years ago
  83. 99cfa1e Multi-DIMMS on AMD ddr3 MCT channel B works. by Kerry She · 14 years ago
  84. 108d30b Trivial syntax correction of AMD mct_ddr3 dir. by Kerry She · 14 years ago
  85. 4793ef1 documented workaround erratum 414, see by Xavi Drudis Ferran · 14 years ago
  86. 213ab94 documented workaround erratum 372, see by Xavi Drudis Ferran · 14 years ago
  87. eb75f65 DDR3 support for AMD Fam10. by Zheng Bao · 14 years ago