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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / mainboard / google / veyron / bootblock.c
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  2. 4bd65e1 rk3288: Allow board-specific APLL (CPU clock) settings by David Hendricks · 9 years ago
  3. dd07ef2 veyron: Unify identical mainboards by Julius Werner · 9 years ago[Renamed from src/mainboard/google/veyron_jerry/bootblock.c]
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. ee426cf google/veyron_*: Increase SPI flash frequency to 24.75MHz by Julius Werner · 9 years ago
  6. 97ab425 rockchip/rk3288: Fix SPI clock divisor calculation by Julius Werner · 9 years ago
  7. 2f37bd6 arm(64): Globally replace writel(v, a) with write32(a, v) by Julius Werner · 10 years ago
  8. 01368ed Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UART by Patrick Georgi · 9 years ago
  9. 0c253b6 rk3288: move reboot_from_watchdog() before rk808 setting by huang lin · 10 years ago
  10. 105f5b7 chromeos: Provide common watchdog reboot support by Julius Werner · 10 years ago
  11. 4d24421 veyron_*: Move PMIC_BUS to a Kconfig variable by David Hendricks · 10 years ago
  12. 908ceef veyron: Fix TPM I2C initialization and sync boards by Julius Werner · 10 years ago
  13. 2460a55 veyron: Trigger hard reset (via GPIO) if last reboot was caused by watchdog by Julius Werner · 10 years ago
  14. df5bf2b rk3288: Move UART initialization to bootblock_mainboard_early_init() by Julius Werner · 10 years ago
  15. 63451c7 veyron_jerry: Port CPU overshoot prevention by Julius Werner · 10 years ago
  16. b262c72 Add google/veyron_jerry board by Katie Roberts-Hoffman · 10 years ago