Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 9631016660423d0585a1 / src / mainboard / google / urara / bootblock.c
  1. 4f3d400 imgtec/pistachio: disable default RPU gate register values by Ionela Voinescu · 9 years ago
  2. 90d1235 mainboard/google/urara: change SYS PLL to 700MHz by Ionela Voinescu · 9 years ago
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 2fdc61a google/urara: use board ID information to set up hardware by Ionela Voinescu · 9 years ago
  6. d99e082 urara: I2C clock and MFIO setup function for all interfaces by Ionela Voinescu · 9 years ago
  7. 38063b0 pistachio: add clock setup for all I2C interfaces by Ionela Voinescu · 9 years ago
  8. 256b1c3 urara: increase drive strength for SPIM1 MFIOs by Ionela Voinescu · 10 years ago
  9. 1d9515f urara: setup I2C0 clock and MFIOs by Ionela Voinescu · 10 years ago
  10. 0f58d0b urara: Reduce MIPS PLL jitter by Ionela Voinescu · 10 years ago
  11. 8b1f23e urara: add clock setup for MIPS CPU, ROM and Ethernet by Ionela Voinescu · 10 years ago
  12. 125427a urara: remove call to printk before UART is initialized by Ionela Voinescu · 10 years ago
  13. b3f666b urara: Configure clocks and MFIOs by Ionela Voinescu · 10 years ago