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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / cpu / intel / haswell / cache_as_ram.inc
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  2. 86091f9 cpu/mtrr.h: Fix macro names for MTRR registers by Alexandru Gagniuc · 9 years ago
  3. df20506 Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig by Martin Roth · 9 years ago
  4. 4a45ec4 x86: Drop -Wa,--divide by Stefan Reinauer · 9 years ago
  5. 5264862 Remove empty lines at end of file by Elyes HAOUAS · 9 years ago
  6. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  7. 1729cd8 x86 romstage: Move stack just below RAMTOP by Kyösti Mälkki · 10 years ago
  8. 4fe9813 src/cpu: Fix spelling of MTTR to MTRR by Paul Menzel · 11 years ago
  9. 8ee04d7 usbdebug: Put ehci_debug_info in CAR_GLOBAL by Kyösti Mälkki · 11 years ago
  10. 7492ec1 haswell: add romstage_after_car() function by Aaron Durbin · 12 years ago
  11. 38d9423 haswell: romstage: pass stack pointer and MTRRs by Aaron Durbin · 12 years ago
  12. 3d0071b haswell: adjust CAR usage by Aaron Durbin · 12 years ago
  13. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago