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coreboot
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9631016660423d0585a1
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src
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cpu
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amd
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family_10h-family_15h
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init_cpus.c
f8549e8
cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setup
by Timothy Pearson
· 9 years ago
346fcb2
cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0
by Timothy Pearson
· 9 years ago
50001b8
northbridge/amd/amdht: Add isochronous setup support
by Timothy Pearson
· 9 years ago
68130f5
amd/amdfam10: Control Fam15h cache partitioning via nvram
by Timothy Pearson
· 9 years ago
a52d5d1
cpu/amd/fam15h: Set up Link Base Channel Buffer Count registers
by Timothy Pearson
· 9 years ago
baa1acd
cpu/amd/fam10h15h: Set up SRI to XCS Token Count registers on Family 15h
by Timothy Pearson
· 9 years ago
71b8f01
cpu/amd/family_10h-family_15h: Set up link XCS token counts on Family 15h
by Timothy Pearson
· 9 years ago
965704a
amd/family_10h-family_15h: Fix poor performance on Family 15h CPUs
by Timothy Pearson
· 9 years ago
0f1553b
nb/amd/amdfam10: Add HyperTransport probe filter support
by Timothy Pearson
· 9 years ago
e536a4d
cpu/amd/fam10h-fam15h: Set northbridge throttle values
by Timothy Pearson
· 9 years ago
0122afb
cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
by Timothy Pearson
· 9 years ago
38508a0
cpu/amd: Fix AMD Family 15h ECC initialization reliability issues
by Timothy Pearson
· 9 years ago
83abd81
cpu/amd: Add CC6 support
by Timothy Pearson
· 9 years ago
730a043
cpu/amd: Add initial AMD Family 15h support
by Timothy Pearson
· 9 years ago
b30d7ed
cpu/amd: Move model_10xxx to family_10h-family_15h
by Timothy Pearson
· 9 years ago
[Renamed from src/cpu/amd/model_10xxx/init_cpus.c]
a73b931
tree: drop last paragraph of GPL copyright header
by Patrick Georgi
· 9 years ago
1c4508e
cpu/amd: Add initial support for AMD Socket G34 processors
by Timothy Pearson
· 9 years ago
fb39f82
cpu/amd/car: Move AP stacks below the BSP stack to free up space
by Timothy Pearson
· 9 years ago
b5e4655
cpu/amd: Detect any conflicts between sysinfo and the stack region
by Timothy Pearson
· 9 years ago
b890a12
Remove address from GPLv2 headers
by Patrick Georgi
· 9 years ago
239c3d3
AMD fam10: Drop RAMINIT_SYSINFO
by Kyösti Mälkki
· 11 years ago
142b52c
AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes
by Kyösti Mälkki
· 11 years ago
88a67f0
AMD boards (non-AGESA): Cleanup earlymtrr.c includes
by Kyösti Mälkki
· 11 years ago
f0a13ce
AMD boards: Fix includes for microcode updates
by Kyösti Mälkki
· 11 years ago
4c3ab73
cpu: Fix spelling
by Martin Roth
· 11 years ago
a46a712
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
by Paul Menzel
· 11 years ago
f8f0062
Some more #if cleanup
by Patrick Georgi
· 12 years ago
e166782
Clean up #ifs
by Patrick Georgi
· 12 years ago
b251753
Change read_option() to a macro that wraps some API uglyness
by Patrick Georgi
· 13 years ago
6bdc83b
Improving BKDG implementation of P-states,
by Xavi Drudis Ferran
· 13 years ago
4c28a6f
Make AMD Fam10h CPU microcode updates optional in Expert mode
by Xavi Drudis Ferran
· 13 years ago
799fed9
Add AMD SB800 southbridge CIMx code.
by Kerry She
· 14 years ago
76e8152
Move the SET_FIDVID* family of configuration options to Kconfig and
by Patrick Georgi
· 14 years ago
f3e8542
reg is only used inside the #if clause, so declare it there. trivial.
by Patrick Georgi
· 14 years ago
1ba2eee
Revision 5966 changed the end of line style of the 3 modified files. This change restores the original end of line style.
by Scott Duplichan
· 14 years ago
af786b6
When debug logging is enabled, a message such as '* AP 02 timed out:02010501'
by Scott Duplichan
· 14 years ago
e5b7507
Remove duplicate line from pci_ids.h.
by Jonathan Kollasch
· 14 years ago
e7a5b76
Move initialization of MMCONF BAR to cache_as_ram setup phase, in order
by Arne Georg Gleditsch
· 14 years ago
d6689ed
Please find appended. This patch gets rid of the %gs magic altogether,
by Arne Georg Gleditsch
· 14 years ago
080ed7c
Trivial - remove stray characters from a comment block.
by Marc Jones
· 14 years ago
6f57b51
Fix all warnings in the tree
by Stefan Reinauer
· 14 years ago
817d754
get rid of even more fam10 and k8 warnings.
by Stefan Reinauer
· 14 years ago
5e33e82
fix some more warnings
by Stefan Reinauer
· 14 years ago
eb50c7d
Re-integrate "USE_OPTION_TABLE" code.
by Edwin Beasant
· 14 years ago
c928a29
Remove another set of includes from Fam10 romstages:
by Patrick Georgi
· 14 years ago
3d5bb23
Move includes to where they are needed. This allows to simplify
by Patrick Georgi
· 14 years ago
075fbe8
Remove a few more warnings from fam10.
by Myles Watson
· 14 years ago
362db61
Cosmetically make init_cpus more similar for fam10 and K8.
by Myles Watson
· 14 years ago
9b43afd
Clean up fidvid files using indent. Remove some special print statements.
by Myles Watson
· 14 years ago
4839e2c
Replace dual_core and quad_core CMOS (nvram) options with multi_core. Fix some white space.
by Myles Watson
· 14 years ago
8f2c616
No warnings day, next round.
by Stefan Reinauer
· 14 years ago
cadefaf
Fix reading HT link offsets.
by Maximilian Thuermer
· 14 years ago
c02b4fc
printk_foo -> printk(BIOS_FOO, ...)
by Stefan Reinauer
· 14 years ago
ed15220
Replace clear_memory with memset.
by Myles Watson
· 14 years ago
38f147e
janitor task: unify and cleanup naming.
by Stefan Reinauer
· 15 years ago
d73c1b5
Define some variables that were not defined. There are a couple left.
by Myles Watson
· 15 years ago
0867062
This patch unifies the use of config options in v2 to all start with CONFIG_
by Stefan Reinauer
· 15 years ago
cbefc23
Maximilian Thuermer found a bug where the HT link capability code was always
by Marc Jones
· 15 years ago
2ee6779
The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
by Carl-Daniel Hailfinger
· 16 years ago
35b5361
Add AMD Fam10 B3 default settings to match AMD example code.
by Marc Jones
· 16 years ago
65e0804
Remove inline from FAM10 CPU initialization functions.
by Marc Jones
· 16 years ago
403b89a
On APs the ClLinesToNbDis was being left enabled from CAR setup.
by Marc Jones
· 16 years ago
8127dc4
Update the FAM10 microcode to current versions.
by Marc Jones
· 16 years ago
da4ce6b
Add early MSR and PCI register initialization.
by Marc Jones
· 16 years ago
7e61e45
Please bear with me - another rename checkin. This qualifies as trivial, no
by Stefan Reinauer
· 17 years ago
8ae8c88
Initial AMD Barcelona support for rev Bx.
by Marc Jones
· 17 years ago