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review.coreboot.org / coreboot / 92646ea3e3456a0a975775a1f5aa5dc011a9b1b6 / src / southbridge / intel / i82801gx / lpc.c
  1. 92646ea sb/intel/i82801gx: Improve code formatting by Elyes HAOUAS · 4 years, 5 months ago
  2. 182dbde src/southbridge: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 5 months ago
  3. 28f727b sb/intel/i82801gx: drop IGD-related NVS variables by Matt DeVillier · 4 years, 5 months ago
  4. 68680dd Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator` by Nico Huber · 4 years, 5 months ago
  5. f3f36fa src (minus soc and mainboard): Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  6. cbf9571 drivers/pc80/rtc: Separate {get|set}_option() prototypes by Kyösti Mälkki · 4 years, 8 months ago
  7. 767de0a sb/intel/i82801gx: Only include SPI code with SPI boot devices by Arthur Heymans · 4 years, 9 months ago
  8. 44da9e7 sb/intel/i82801gx,ix,jx: Move HAVE_SMI_HANDLER conditional by Kyösti Mälkki · 4 years, 10 months ago
  9. 7630803 sb/intel: Remove ENABLE_ACPI_MODE_IN_COREBOOT by Kyösti Mälkki · 4 years, 10 months ago
  10. 51b75ae device: Use scan_static_bus() over scan_lpc_bus() by Nico Huber · 5 years ago
  11. c73c923 sb/intel/nm10: Fix enabling HPET by Arthur Heymans · 4 years, 11 months ago
  12. 83d6a8a intel/i82801gx,i82801jx: Rename lock_smm() by Kyösti Mälkki · 5 years ago
  13. b429c5b sb/intel/i82801gx: Use common final SPI OPs setup by Arthur Heymans · 5 years ago
  14. 742df5a sb/intel/i82801gx: Include chip.h directly by Arthur Heymans · 5 years ago
  15. 0c22d2f {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro by Elyes HAOUAS · 6 years ago
  16. 7118701 sb/intel/i82801gx/lpc: Use {read,write}_pmbase32 and lpc_get_pmbase by Elyes HAOUAS · 6 years ago
  17. 4a0f071 {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() by Subrata Banik · 5 years ago
  18. cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
  19. f1b58b7 device/pci: Fix PCI accessor headers by Kyösti Mälkki · 5 years ago
  20. 0d4de2a ACPI: Rename FADT model and set it to zero by Elyes HAOUAS · 5 years ago
  21. 84fdda3 nb/intel/pineview: Use parallel MP init by Arthur Heymans · 6 years ago
  22. f266932 nb/intel/i945: Use parallel MP init by Arthur Heymans · 6 years ago
  23. 744d6bd sb/intel: Check for NULL-return of pcidev_on_root() by Nico Huber · 6 years ago
  24. 9faae2b Kconfig: Unify power-after-failure options by Nico Huber · 6 years ago
  25. c70eed1 device: Use pcidev_on_root() by Kyösti Mälkki · 6 years ago
  26. d2b9ec1 src: Remove unneeded include "{arch,cpu}/cpu.h" by Elyes HAOUAS · 6 years ago
  27. 38f1d13 src/{sb/intel,mb/google/auron}: Don't use device_t by Elyes HAOUAS · 6 years ago
  28. a8a9f34 sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables by Arthur Heymans · 7 years ago
  29. 3664647 sb/intel/i82801gx: Add the option to lock the platform by Arthur Heymans · 7 years ago
  30. 9966703 sb/intel/i82801gx: Get rid of device_t by Elyes HAOUAS · 6 years ago
  31. 7a1a3ad southbridge/intel: add IS_ENABLED() around Kconfig symbol references by Martin Roth · 7 years ago
  32. 3f111b0 southbridge/intel/i82801gx: Fix problems found by checkpatch.pl by Arthur Heymans · 7 years ago
  33. 035df00 src/southbridge: Remove whitespace after sizeof by Elyes HAOUAS · 8 years ago
  34. ba28e8d src/southbridge: Code formating by Elyes HAOUAS · 8 years ago
  35. 2ed0aa2 Correct some common spelling mistakes by Martin Roth · 9 years ago
  36. ef33e03 southbridge/intel: Use i82801gx code for NM10 by Damien Zammit · 9 years ago
  37. d5d94ea intel/i945: Consolidate MADT handling by Vladimir Serbinenko · 10 years ago
  38. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  39. a90dad1 device_ops: add device_t argument to acpi_inject_dsdt_generator by Alexander Couzens · 9 years ago
  40. d0e212c devicetree: Discriminate device ops scan_bus() by Kyösti Mälkki · 9 years ago
  41. f119f08 i82801gx: Reserve LPC decodes. by Vladimir Serbinenko · 10 years ago
  42. dd2bc3f igd.asl rewrite by Vladimir Serbinenko · 10 years ago
  43. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  44. b85a87b intel SMI handlers: Refactor GPI SMI/SCI routing by Kyösti Mälkki · 10 years ago
  45. 06ef046 global: Refactor get_option usage by Varad Gautam · 9 years ago
  46. bde6d30 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer by Kevin Paul Herbert · 10 years ago
  47. 385743a i945: Consolidate common GNVS init by Vladimir Serbinenko · 10 years ago
  48. 1bad88e i82801gx: Move to implicit length patching by Vladimir Serbinenko · 10 years ago
  49. ab83ef0 i82801gx: Handle whole FADT in southbridge. by Vladimir Serbinenko · 10 years ago
  50. b3f08c6 cmos: Rename the CMOS related functions. by Gabe Black · 10 years ago
  51. c21e073 i945: Consolidate FADT code by Vladimir Serbinenko · 10 years ago classic-2014.10
  52. 0e64617 i945: Convert to per-device ACPI by Vladimir Serbinenko · 10 years ago
  53. c3ed886 intel boards: Use acpi_is_wakeup_s3() by Kyösti Mälkki · 10 years ago
  54. 72dccce global: Fix usage of get_option() to make use of CB_CMOS_ codes by Alexandru Gagniuc · 11 years ago
  55. ddddf15 Intel 82801Gx: LPC: Unify I/O APIC setup by Paul Menzel · 11 years ago
  56. 526a46e Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 by Paul Menzel · 11 years ago
  57. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  58. 1cca340 Use defines for some i82801ex/gx registers by Kyösti Mälkki · 11 years ago
  59. 906f9ae i82801gx: Add setting for C4onC3 mode by Sven Schnelle · 13 years ago
  60. ab87254 use acpi.h include instead of manually adding acpi_slp_type. by Stefan Reinauer · 13 years ago
  61. e261807 i82801gx: enable ACPI during S3 resume by Sven Schnelle · 13 years ago
  62. f4dc1a7 SMM: add defines for APM_CNT register by Sven Schnelle · 13 years ago
  63. cadc545 SMM for AMD K8 Part 1/2 by Stefan Reinauer · 14 years ago
  64. 836ae29 first round name simplification. drop the <component>_ prefix. by stepan · 14 years ago[Renamed from src/southbridge/intel/i82801gx/i82801gx_lpc.c]
  65. 74d1a6e We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it. by Uwe Hermann · 14 years ago
  66. 7eac445 Always enable parent resources before child resources. by Myles Watson · 14 years ago
  67. c02b4fc printk_foo -> printk(BIOS_FOO, ...) by Stefan Reinauer · 14 years ago
  68. de3206a This is a general cleanup patch by Stefan Reinauer · 14 years ago
  69. 7a3d095 by Stefan Reinauer · 15 years ago
  70. aca6ec6 Kontron 986LCD-M update by Stefan Reinauer · 15 years ago
  71. 109ab31 drop extra whitespace at end of line for i945 + ICH7 (trivial) by Stefan Reinauer · 15 years ago
  72. dec1b47 Add some more CONFIG_* prefixes that were missing. by Patrick Georgi · 15 years ago
  73. 573f7d4 Intel ICH7 updates by Stefan Reinauer · 15 years ago
  74. 85a94f6 Rename some preprocessor symbols. I have no idea why by Patrick Georgi · 15 years ago
  75. 29cc9ed Move the v3 resource allocator to v2. by Myles Watson · 15 years ago
  76. 0867062 This patch unifies the use of config options in v2 to all start with CONFIG_ by Stefan Reinauer · 15 years ago
  77. a9c5ea0 Revert "CMOS: Add set_option and rework get_option." by Luc Verhaegen · 15 years ago
  78. 9ceae90 CMOS: Add set_option and rework get_option. by Luc Verhaegen · 15 years ago
  79. a8e1168 This patch contains some significant updates to the i82801gx component and will by Stefan Reinauer · 15 years ago
  80. 54309d6 Update Kontron board by Stefan Reinauer · 16 years ago
  81. 269563a First shot at factoring SMM code into generic parts and southbridge specific by Stefan Reinauer · 16 years ago
  82. 556801e The enable_hpet() code in intel/i82801gx will not work with the by Uwe Hermann · 16 years ago
  83. 5d7a1c8 Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines. by Uwe Hermann · 16 years ago
  84. bddc693 i945/ICH7: Use #defines from pci_ids.h (trivial). by Uwe Hermann · 16 years ago
  85. debb11f Support for the Intel ICH7 southbridge. by Stefan Reinauer · 16 years ago