Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 91d1e76fd168defce4132d1e308b68a2013a89df / src / include / cpu / intel
  1. a4ffe9d intel post-car: Separate files for setup_stack_and_mtrrs() by Kyösti Mälkki · 8 years ago
  2. 40d7a45 cpu/intel: Add MSR to support enabling turbo frequency by Shaunak Saha · 8 years ago
  3. 362180a soc/intel/apollolake: Disable Monitor and Mwait feature by Venkateswarlu Vinjamuri · 8 years ago
  4. c5400ef intel: Drop old romstage main() without asmlinkage by Kyösti Mälkki · 8 years ago
  5. e325b22 intel: Fix romstage main() with asmlinkage by Kyösti Mälkki · 8 years ago
  6. a02bb65 cpu/intel/microcode: allow microcode to be loaded in romstage by Aaron Durbin · 9 years ago
  7. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  8. 30b755b Add SoC specific microcode update check in ramstage by Rizwan Qureshi · 9 years ago
  9. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  10. 033bb4b acpi: Generate valid ACPI processor objects by Timothy Pearson · 10 years ago
  11. a0a3727 intel/cpu: rename car.h to romstage.h by Aaron Durbin · 10 years ago
  12. 1ab2027 Intel: Add common header file for CAR setup by Edward O'Callaghan · 10 years ago
  13. 2c38f50 cpu/intel: Make all Intel CPUs load microcode from CBFS by Alexandru Gagniuc · 11 years ago
  14. 66e0c4c cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS by Alexandru Gagniuc · 11 years ago
  15. 3f5f6d8 Drop prototype guarding for romcc by Stefan Reinauer · 11 years ago
  16. d46161e intel/microcode.h: Fix typo in comment: micr*o*code by Paul Menzel · 11 years ago
  17. 98ffb42 intel microcode: split up microcode loading stages by Aaron Durbin · 12 years ago
  18. 8cc8468 Intel: Replace MSR 0xcd with MSR_FSB_FREQ by Patrick Georgi · 12 years ago
  19. 644e83b speedstep: Deduplicate some MSR identifiers by Patrick Georgi · 12 years ago
  20. a74af56 Overhaul speedstep code by Nico Huber · 12 years ago
  21. 41392df Merge cpu/intel/acpi.h into cpu/intel/speedstep.h by Nico Huber · 12 years ago
  22. 00b579a buildsystem: Make CPU microcode updating more configurable by Alexandru Gagniuc · 12 years ago
  23. 537b4e0 Add code to read Intel microcode from CBFS by Vadim Bendebury · 12 years ago
  24. 9ed1456 Intel CPUs: execute microcode update only once per core by Kyösti Mälkki · 12 years ago
  25. 3f8989e Revamp Intel microcode update code by Stefan Reinauer · 12 years ago
  26. 2bdfb48 Fixes and Sandybridge support for lapic cpu init by Stefan Reinauer · 12 years ago
  27. ea37a21 Add support for Intel Turbo Boost feature by Stefan Reinauer · 12 years ago
  28. 1ac19e2 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. by Keith Hui · 13 years ago
  29. 2a27b20 factor out cpu power management base into a separate file. And fix a bug in by Stefan Reinauer · 14 years ago
  30. d491769 For completeness sake: License header. by Patrick Georgi · 14 years ago
  31. 361bd10 Move Intel power management related defines to some central location. by Patrick Georgi · 14 years ago
  32. c598330 fix compiler warnings (trivial) by Stefan Reinauer · 16 years ago
  33. c84c190 - Renamed cpu header files by Eric Biederman · 20 years ago