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review.coreboot.org / coreboot / 8e9906c19abf91d20a75ac24cfc7bd5637c2fbb5 / src / northbridge / intel / gm45 / chip.h
  1. 98c9257 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm by Arthur Heymans · 1 year, 9 months ago
  2. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  3. 4b42983 src/northbridge: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 5 months ago
  4. f3f36fa src (minus soc and mainboard): Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  5. 20cb85f nb/intel/gm45: Set display backlight according to EDID string by Arthur Heymans · 7 years ago
  6. 12bed26 nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency by Arthur Heymans · 8 years ago
  7. 266a1f7 nb/intel/raminit (native): Read PCI mmio size from devicetree by Patrick Rudolph · 8 years ago
  8. b851cc6 nb/intel/gm45: Backport configuration of panel power timings by Nico Huber · 9 years ago
  9. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  10. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  11. a71bdc3 intel/gma: consolidate vbt code by Vladimir Serbinenko · 10 years ago
  12. 8801011 intel/gm45: native gfx init. by Vladimir Serbinenko · 10 years ago
  13. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  14. 2efc880 intel/gm45: new northbridge by Patrick Georgi · 12 years ago