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review.coreboot.org / coreboot / 89ae6b8fc2901b56dd1839a2d569493ce668a32c / src / northbridge / intel / sandybridge / raminit_sandy.c
  1. 89ae6b8 nb/intel/sandybridge: Use cached CPUID by Angel Pons · 4 years, 5 months ago
  2. 143309f nb/intel/sandybridge: Remove oddball `- 1` in tRFC by Angel Pons · 4 years, 5 months ago
  3. 7c49cb8 nb/intel/sandybridge: Tidy up code and comments by Angel Pons · 4 years, 5 months ago
  4. f3f36fa src (minus soc and mainboard): Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  5. 8852188 nb/intel/sandybridge: Add a bunch of MCHBAR defines by Angel Pons · 4 years, 7 months ago
  6. 1aba2a3 nb/intel/sandybridge: Make MCHBAR arithmetics consistent by Angel Pons · 4 years, 7 months ago
  7. f369e60 northbridge/intel: Remove unneeded includes by Elyes HAOUAS · 6 years ago
  8. dabebc3 nb/intel/sandybridge: support more XMP timings by Dan Elkouby · 6 years ago
  9. dcd3cef nb/intel/sandybridge: Improve CAS freq selection by Arthur Heymans · 7 years ago
  10. 77eaba3 nb/intel/sandybridge/raminit: Use Ivy Bridge specific values by Patrick Rudolph · 8 years ago
  11. 50db9c9 nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings by Arthur Heymans · 7 years ago
  12. 305035c nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge by Patrick Rudolph · 8 years ago