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review.coreboot.org / coreboot / 83067610f754f89025bf781cdf8857135e946b03 / src / soc / intel / broadwell / pcie.c
  1. 8306761 broadwell: Fix PCIe ports programming sequences to enable HSIOPC by Wenkai Du · 10 years ago
  2. e8f3664 Broadwell: Synchronization with FRC for Root Port Power Management by Kenji Chen · 10 years ago
  3. 4ee4bd5 broadwell: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  4. 94fea49 Broadwell: Fix PCIe L1 Sub-State capability ID not filled. by Kenji Chen · 10 years ago
  5. b71d9b8 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. by Kenji Chen · 10 years ago
  6. e383feb Broadwell: Synchronize for power management with FRC by Kenji Chen · 10 years ago
  7. c373f50 Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRC by Kenji Chen · 10 years ago
  8. 8ef55ee Broadwell: Revise programming flow for write-once registers by Kenji Chen · 10 years ago
  9. 87d4a20 broadwell: Configure IOSF Port and Grant Count by Kenji Chen · 10 years ago
  10. 642e598 broadwell: Update PCIe configuration to follow BWG by Kane Chen · 10 years ago
  11. 4613472 broadwell: Fix some errors in selftest by Kane Chen · 10 years ago
  12. 4fef5a2 broadwell: Apply pcie updates from 2.1.0 ref code by Kane Chen · 10 years ago
  13. 446fb8e broadwell: Misc updates from 2.1.0 ref code by Duncan Laurie · 10 years ago
  14. de7ed6f intel/broadwell: Spelling fixes by Martin Roth · 10 years ago
  15. c88c54c broadwell: add new intel SOC by Duncan Laurie · 10 years ago