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review.coreboot.org / coreboot / 7cba1c486beb9287dc563784904d2a8e0235340a / src / soc / intel / broadwell / pch / pcie.c
  1. 7cba1c4 treewide: Remove duplicated include <device/pci.h> by Elyes Haouas · 1 year, 5 months ago
  2. 8b8ada6 /: Remove extra space after comma by Elyes Haouas · 1 year, 8 months ago
  3. 43b7f41 src: Make PCI ID define names shorter by Felix Singer · 2 years, 4 months ago
  4. af4bd56 sb/intel: Use `bool` for PCIe coalescing option by Angel Pons · 2 years, 6 months ago
  5. c7ca0f2 soc/intel/broadwell/pcie.c: Simplify AND-mask by Angel Pons · 2 years, 10 months ago
  6. c423ce2 soc/intel/broadwell: Use Lynx Point IOBP code by Angel Pons · 3 years, 3 months ago
  7. 968ef75 pciexp_device: Rewrite LTR configuration by Nico Huber · 3 years, 4 months ago
  8. a768dea device: Give `pci_ops.set_L1_ss_latency` a proper name by Nico Huber · 3 years, 4 months ago
  9. 733f03d soc/intel/broadwell/pch: Prepare to drop `gpio.h` by Angel Pons · 3 years, 5 months ago
  10. 6b486e1 soc/intel/broadwell/pch: Simplify PCI RMW operations by Angel Pons · 3 years, 8 months ago
  11. 9d733de soc/intel/broadwell: Use Haswell CPU headers by Angel Pons · 3 years, 8 months ago
  12. c200e8c7 soc/intel/broadwell: Move PCH code into pch subdir by Angel Pons · 3 years, 9 months ago[Renamed from src/soc/intel/broadwell/pcie.c]
  13. 3cc2c38 soc/intel/broadwell: Separate PCH in devicetree by Angel Pons · 3 years, 9 months ago
  14. d5689dd soc/intel/broadwell/pcie.c: Add some null checks by Angel Pons · 3 years, 10 months ago
  15. 2ead363 soc/intel/broadwell: Align cosmetics with Haswell/Lynx Point by Angel Pons · 3 years, 10 months ago
  16. b82b431 src: Never set ISA Enable on PCI bridges by Angel Pons · 4 years ago
  17. 6dd466c soc/intel/broadwell/pcie.c: Drop dead code by Angel Pons · 4 years ago
  18. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 2 months ago
  19. b887adf soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register by Elyes HAOUAS · 4 years, 2 months ago
  20. f94ac9a soc/intel/broadwell: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 3 months ago
  21. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 4 months ago
  22. df128a5 intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL by Kyösti Mälkki · 4 years, 10 months ago
  23. 8950cfb soc/intel: Use config_of() by Kyösti Mälkki · 5 years ago
  24. ed6996f device/pciexp_device: Convert LTR non-snoop/snoop value into common macro by Subrata Banik · 5 years ago
  25. 15ccbf0 {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() by Subrata Banik · 5 years ago
  26. cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
  27. 040aff2 soc/intel/broadwell: Get rid of device_t by Elyes HAOUAS · 6 years ago
  28. 7161678 intel/broadwell: Add option to enable/disable the PCIe AER capability by Youness Alaoui · 6 years ago
  29. 1f64b01 intel/broadwell: If L1 Sub state is disabled, do not set capability by Youness Alaoui · 6 years ago
  30. e56189c pci: Move inline PCI functions to pci_ops.h by Patrick Rudolph · 6 years ago
  31. 6ef5192 soc/intel/broadwell: Fix other issues detected by checkpatch by Lee Leahy · 7 years ago
  32. 23602df soc/intel/broadwell: Add int to unsigned by Lee Leahy · 7 years ago
  33. 48c389e PCI ops: Define read-modify-write routines globally by Kyösti Mälkki · 11 years ago
  34. b4a45dc intel PCI ops: Remove explicit PCI MMCONF access by Kyösti Mälkki · 11 years ago
  35. e8f2ef5 intel/broadwell: fix typo by Patrick Georgi · 8 years ago
  36. 2b2ff7f soc/intel/broadwell: Init var before use, only use when needed by Martin Roth · 9 years ago
  37. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  38. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  39. b14c067 broadwell: Set PCIe replay timeout to 0xD by Duncan Laurie · 9 years ago
  40. cad2b7b broadwell: Skip steps when disabling PCIe port by Duncan Laurie · 9 years ago
  41. 8306761 broadwell: Fix PCIe ports programming sequences to enable HSIOPC by Wenkai Du · 10 years ago
  42. e8f3664 Broadwell: Synchronization with FRC for Root Port Power Management by Kenji Chen · 10 years ago
  43. 4ee4bd5 broadwell: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  44. 94fea49 Broadwell: Fix PCIe L1 Sub-State capability ID not filled. by Kenji Chen · 10 years ago
  45. b71d9b8 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. by Kenji Chen · 10 years ago
  46. e383feb Broadwell: Synchronize for power management with FRC by Kenji Chen · 10 years ago
  47. c373f50 Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRC by Kenji Chen · 10 years ago
  48. 8ef55ee Broadwell: Revise programming flow for write-once registers by Kenji Chen · 10 years ago
  49. 87d4a20 broadwell: Configure IOSF Port and Grant Count by Kenji Chen · 10 years ago
  50. 642e598 broadwell: Update PCIe configuration to follow BWG by Kane Chen · 10 years ago
  51. 4613472 broadwell: Fix some errors in selftest by Kane Chen · 10 years ago
  52. 4fef5a2 broadwell: Apply pcie updates from 2.1.0 ref code by Kane Chen · 10 years ago
  53. 446fb8e broadwell: Misc updates from 2.1.0 ref code by Duncan Laurie · 10 years ago
  54. de7ed6f intel/broadwell: Spelling fixes by Martin Roth · 10 years ago
  55. c88c54c broadwell: add new intel SOC by Duncan Laurie · 10 years ago