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review.coreboot.org / coreboot / 7c49cb8f9ca86e791c392da40e7f0d3cb7ed47f3 / src / northbridge / intel / sandybridge / chip.h
  1. 7c49cb8 nb/intel/sandybridge: Tidy up code and comments by Angel Pons · 4 years, 4 months ago
  2. f3f36fa src (minus soc and mainboard): Remove copyright notices by Patrick Georgi · 4 years, 4 months ago
  3. 5709e03 nb/intel/sandybridge: Migrate MRC settings to devicetree by Patrick Rudolph · 5 years ago
  4. 266a1f7 nb/intel/raminit (native): Read PCI mmio size from devicetree by Patrick Rudolph · 8 years ago
  5. d7ee9dd northbridge/intel: add missing #include guards by Iru Cai · 8 years ago
  6. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  7. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  8. 8b2c8f1 sandybridge/raminit: Get max mem clock from devicetree by Alexandru Gagniuc · 9 years ago
  9. a71bdc3 intel/gma: consolidate vbt code by Vladimir Serbinenko · 10 years ago
  10. 1783a3c ivybridge: LVDS gfx init. by Vladimir Serbinenko · 10 years ago
  11. 234781e northbridge: Trivial - drop trailing blank lines at EOF by Edward O'Callaghan · 10 years ago
  12. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  13. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  14. dd585b8 Update ivybridge graphics initialization by Duncan Laurie · 12 years ago
  15. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago