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review.coreboot.org / coreboot / 77051e061f1ea6e2aa307ef867740ce2f73d282c / src
  1. 77051e0 mainboard/intel/galileo: Add FSP 2.0 Kconfig support by Lee Leahy · 8 years ago
  2. 38e0cc0 soc/intel/quark: Add header files for FSP 2.0 by Lee Leahy · 8 years ago
  3. 01728bb soc/intel/quark: Prepare for FSP2.0 support by Lee Leahy · 8 years ago
  4. 3d0e3cf soc/intel/quark: Initialize MTRRs in bootblock by Lee Leahy · 8 years ago
  5. 14d0926 soc/intel/quark: Remove use of EDK-II macros and data types by Lee Leahy · 8 years ago
  6. 1cfb555 fsp_broadwell_de: Add DMAR table to ACPI by Werner Zeh · 8 years ago
  7. 21a5bff ACPI: Add code to create root port entry in DMAR table by Werner Zeh · 8 years ago
  8. d4d7695 ACPI: Add code to include ATSR structure in DMAR table by Werner Zeh · 8 years ago
  9. b0afbad mainboard/intel/galileo: Remove use of EDK-II macros & data types by Lee Leahy · 8 years ago
  10. d87d8ea soc/intel/quark: Make ramstage relocatable by Lee Leahy · 8 years ago
  11. b20d4ba drivers/intel/fsp2_0: Update the debug levels by Lee Leahy · 8 years ago
  12. 94e502b drivers/intel/fsp2_0: Remove fsp_print_upd_info declaration by Lee Leahy · 8 years ago
  13. 37b5ef2 drivers/intel/fsp2_0: Disable display of FSP header by Lee Leahy · 8 years ago
  14. 806fa24 drivers/intel/fsp2_0: Handle FspNotify calls by Lee Leahy · 8 years ago
  15. 9671faa drivers/intel/fsp2_0: FSP driver handles all FSP errors by Lee Leahy · 8 years ago
  16. 52d0c68 drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit by Lee Leahy · 8 years ago
  17. ac3b0a6 drivers/intel/fsp2_0: Add display HOB support by Lee Leahy · 8 years ago
  18. e6f2f74 drivers/intel/fsp2_0: Add UPD display support by Lee Leahy · 8 years ago
  19. 0a38b22 drivers/intel/fsp2_0: Monitor FSP setting of MTRRs by Lee Leahy · 8 years ago
  20. cc5be8b arch/riscv: Add include/arch/barrier.h by Jonathan Neuschäfer · 8 years ago
  21. 1b41f4d google/lars & intel/kunimitsu: Disable EC build by Martin Roth · 8 years ago
  22. 145796e superio/fintek/f81866d: Add support for UART 3/4 by Fabian Kunkel · 8 years ago
  23. 5976143 google/reef: Add pull up 20K for LPC SERIRQ by Kane Chen · 8 years ago
  24. d5817c8 intel/amenia: Add GPIO changes to assert SLP_S0/Reset signal by Shankar, Vaibhav · 8 years ago
  25. 67d1697 soc/intel/apollolake: Add iosstate macros for GPIO by Shankar, Vaibhav · 8 years ago
  26. 5aea588 drivers/fsp2_0: Increment boot count for non-S3 boot by Furquan Shaikh · 8 years ago
  27. 8d66bee intel/apollolake: Enable upper CMOS bank in bootblock by Furquan Shaikh · 8 years ago
  28. 5e61233 elog: Include declarations for boot count functions unconditionally by Furquan Shaikh · 8 years ago
  29. 672df16 drivers/intel/fsp2_0: Display FSP calls and status by Lee Leahy · 8 years ago
  30. 48e0792 i2c/w83795: Fix chip type message by Patrick Georgi · 8 years ago
  31. 47f7b0e amd/amdfam10: eliminate dead code by Patrick Georgi · 8 years ago
  32. 8c8403f console: Drop leftover struct console_driver by Kyösti Mälkki · 8 years ago
  33. b168db7 intel/skylake: Fix UART build options by Furquan Shaikh · 8 years ago
  34. 0f2025d intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano by Prabal Saha · 8 years ago
  35. 6e8233a soc/intel/quark: Enable use of hard reset by Lee Leahy · 8 years ago
  36. aac31ca soc/intel/common: Fix build error in reset.c by Lee Leahy · 8 years ago
  37. 0cd338e Remove non-ascii & unprintable characters by Martin Roth · 8 years ago
  38. bb9722b Add newlines at the end of all coreboot files by Martin Roth · 8 years ago
  39. 049b462 arch/x86: Enable postcar console by Lee Leahy · 8 years ago
  40. f67e2cf arch/x86: Display MTRRs after MTRR update in postcar by Lee Leahy · 8 years ago
  41. 64f38ac siemens/sitemp_g1p1: Fix typo by Patrick Georgi · 8 years ago
  42. 4c18de2 soc/intel/common: Enable MTRR display during bootblock & postcar by Lee Leahy · 8 years ago
  43. 0c1843a soc/intel/quark: Fix car_stage_entry routine name. by Lee Leahy · 8 years ago
  44. 41b3196 mainboard/bap/ode_e20XX: Enable UART 3/4 in devicetree by Fabian Kunkel · 8 years ago
  45. 8cab72e mainboard/bap/ode_e20XX: Add different DDR3 clk settings by Fabian Kunkel · 8 years ago
  46. 1f9c07f mainboard/bap/ode_e20XX: Change PCIe lines by Fabian Kunkel · 8 years ago
  47. 449fb9b superio/nuvoton: Add Nuvoton NCT6791D by Omar Pakker · 8 years ago
  48. 2a60026 src/vboot: Capitalize RAM and CPU by Elyes HAOUAS · 8 years ago
  49. 91e0e3c src/lib: Capitalize ROM, RAM, NVRAM and CPU by Elyes HAOUAS · 8 years ago
  50. 7753731 src/drivers: Capitalize CPU, RAM and ACPI by Elyes HAOUAS · 8 years ago
  51. 038e724 src/soc: Capitalize CPU, ACPI, RAM and ROM by Elyes HAOUAS · 8 years ago
  52. f9e7d1b src/acpi: Capitalize ACPI and SATA by Elyes HAOUAS · 8 years ago
  53. 2660a13 sunw/ultra40m2: Fix handling non-existence of a device by Patrick Georgi · 8 years ago
  54. c091604 sis/sis966: fix typo by Patrick Georgi · 8 years ago
  55. 21ce6ef sis/sis966: don't store a 32bit value in a 16bit variable by Patrick Georgi · 8 years ago
  56. e8f2ef5 intel/broadwell: fix typo by Patrick Georgi · 8 years ago
  57. 90ed31b intel/skylake: Enable signalling of error condition by Patrick Georgi · 8 years ago
  58. bce1807 google/reef: Update chromeos.fmd RO_SECTION by Furquan Shaikh · 8 years ago
  59. b97cf79 intel/amenia: Enable DPTF in mainboard by Shaunak Saha · 8 years ago
  60. 57f221e google/reef: Enable DPTF in mainboard by Shaunak Saha · 8 years ago
  61. c663a1f gigabyte/ga_2761gxdk: Remove comment *endif* by Paul Menzel · 8 years ago
  62. 95fe8fb mainboard: Format irq_tables.c by Paul Menzel · 8 years ago
  63. 14caed8 build system: really disable building CrEC when not needed by Patrick Georgi · 8 years ago
  64. 777ea89 src/arch: Capitalize CPU, RAM and ROM by Elyes HAOUAS · 8 years ago
  65. 45de1fe src/Kconfig: Capitalize ROM by Elyes HAOUAS · 8 years ago
  66. fa640a2 src/device: Capitalize CPU, RAM and ROM by Elyes HAOUAS · 8 years ago
  67. d82be92 src/cpu: Capitalize CPU by Elyes HAOUAS · 8 years ago
  68. 918535a src/include: Capitalize CPU, RAM and ROM by Elyes HAOUAS · 8 years ago
  69. 1bcd7fc src/southbridge: Capitalize CPU, RAM and ROM by Elyes HAOUAS · 8 years ago
  70. 15279a9 src/northbridge: Capitalize CPU, RAM and ROM by Elyes HAOUAS · 8 years ago
  71. 585d1a0 src/cpu: Capitalize ROM and RAM by Elyes HAOUAS · 8 years ago
  72. 9071670 nvidia/tegra124: Adjust memlayout to Chrome OS toolchain by Stefan Reinauer · 8 years ago
  73. 08492f7 google/gale: Change board ID definition. by Kan Yan · 8 years ago
  74. 5ae61d9 Update degree symbol to utf-8 encoding in comments by Martin Roth · 8 years ago
  75. 4c72d36 Remove extra newlines from the end of all coreboot files. by Martin Roth · 8 years ago
  76. 828e73e intel/wifi: Include conditionally in the build by Kyösti Mälkki · 8 years ago
  77. cf05183 mainboard/bap/ode_e21XX: Add board support by Fabian Kunkel · 8 years ago
  78. 171e2c9 mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus by Fabian Kunkel · 8 years ago
  79. b0f8151 chromeos mainboards: remove chromeos.asl by Aaron Durbin · 8 years ago
  80. 212820c google/reef: Use GPE0_DW1_15 as wake signal for touchpad by Furquan Shaikh · 8 years ago
  81. 6e37e90 soc/intel/apollolake: Include gpe.h in chip.h by Furquan Shaikh · 8 years ago
  82. ce37e47 skylake: fix VSDIO is at 0.8V when SDCard is not inserted by Zhuo-hao.Lee · 8 years ago
  83. ec2947f soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume by Abhay Kumar · 8 years ago
  84. 3707fc2 google/gru & kevin: Update DRAM configuration by Lin Huang · 8 years ago
  85. df5ead9 rockchip/rk3399: sdram: correct controller vref setting by Lin Huang · 8 years ago
  86. 47bd2d9 drivers/intel/fsp2_0: Update the copyrights by Lee Leahy · 8 years ago
  87. ab88c7d google/reef: Write protect GPIO relative to bank offset by Susendra Selvaraj · 8 years ago
  88. df12d19 soc/intel/apollolake: Update FSP Header files for version 146_30 by Brandon Breitenstein · 8 years ago
  89. cd9e1e4 intel/apollolake: Update gnvs for dptf by Shaunak Saha · 8 years ago
  90. 5dd2b18 intel/apollolake: Add soc specific DPTF values by Shaunak Saha · 8 years ago
  91. 44887c3 intel/common: Add ASL code for DPTF by Shaunak Saha · 8 years ago
  92. 2098778 intel/common/opregion.c: only write 16 bytes to 16 byte field by Martin Roth · 8 years ago
  93. 8e63017 arch/riscv: Refactor bootblock.S by Jonathan Neuschäfer · 8 years ago
  94. 62bd9f9 arch/riscv: Only initialize virtual memory if it's available by Jonathan Neuschäfer · 8 years ago
  95. 0cc02ef arch/riscv: Remove spinlock code from atomic.h by Jonathan Neuschäfer · 8 years ago
  96. a90f41b intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init by Subrata Banik · 8 years ago
  97. 89f6d60 skylake/devicetree: Add LPC EC decode range by Subrata Banik · 8 years ago
  98. 50b9258 skylake/mainboard: Define mainboard hook in bootblock by Subrata Banik · 8 years ago
  99. e4a8537 soc/intel/skylake: Add C entry bootblock support by Subrata Banik · 8 years ago
  100. 68d5d8b soc/intel/skylake: Do cache as ram and prepare for C entry by Subrata Banik · 8 years ago