Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 76f8dbc4f70469e0b5913796d6130e85df1cdd77 / src / device / dram / ddr3.c
  1. 76f8dbc device/dram/ddr3: add FTB timings by Nicola Corna · 8 years ago
  2. 378d79e device/dram/ddr3: Fix calculation CRC16 of SPD by Kyösti Mälkki · 8 years ago
  3. 7dc4b84 device/dram/ddr3: Calculate CRC16 of SPD unique identifier by Kyösti Mälkki · 8 years ago
  4. 66a98ee device/dram/ddr3: fix debug output by Patrick Rudolph · 8 years ago
  5. 0769159 src/device/dram/ddr3: Parse additional information by Patrick Rudolph · 8 years ago
  6. bd1fdc6 nb/intel/sandybridge/raminit: Add XMP support by Patrick Rudolph · 9 years ago
  7. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  8. 78c6e3e ddr3: add missing newline by Patrick Rudolph · 9 years ago
  9. 8c63935 ddr3: Fix SPD CRC calculation by Patrick Rudolph · 9 years ago
  10. 98b698c src/device: Doxygen fixes by Martin Roth · 10 years ago
  11. 0e675f7 ddr3: Plumber DIMM type to parsed structure. by Vladimir Serbinenko · 10 years ago
  12. 31cef1f device/dram/ddr3.c: Fix sizeof on array func param overflow by Edward O'Callaghan · 10 years ago
  13. 7686a56 sandy/ivybridge: Native raminit. by Vladimir Serbinenko · 10 years ago
  14. 4c37e58 device/dram/ddr3: Move CRC calculation in a separate function by Alexandru Gagniuc · 11 years ago
  15. 63373ed device: Fix spelling by Martin Roth · 11 years ago
  16. 78706fd DDR3: Add utilities for creating MRS commands by Alexandru Gagniuc · 11 years ago
  17. f97ff3f dram: Add utilities for decoding DDR3 SPDs by Alexandru Gagniuc · 11 years ago