Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 76c3700f02f79b49fec30d6ef18d336f122cbf50 / src / northbridge / intel
  1. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago
  2. e7ae96f Add Intel Panther Point USB3 initialization by Marc Jones · 12 years ago
  3. 41dd3db Intel e7505: provide get_top_of_ram by Kyösti Mälkki · 12 years ago
  4. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  5. fd611f9 Drop CONFIG_WRITE_HIGH_TABLES by Stefan Reinauer · 11 years ago
  6. 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster by Stefan Reinauer · 12 years ago
  7. 4aff445 sconfig: rename pci_domain -> domain by Stefan Reinauer · 12 years ago
  8. 600784e spi.h: Rename the spi.h to spi-generic.h by Zheng Bao · 12 years ago
  9. 8cc8468 Intel: Replace MSR 0xcd with MSR_FSB_FREQ by Patrick Georgi · 12 years ago
  10. 6fe0cab Extend CBFS to support arbitrary ROM source media. by Hung-Te Lin · 12 years ago
  11. 816e9d1 Support for Celeron 1007U by Stefan Reinauer · 12 years ago
  12. 5079a0d Remove assembly coded log2 function by Ronald G. Minnich · 12 years ago
  13. 721265b Drop driver-y from GM45/ICH9/RK9 by Stefan Reinauer · 12 years ago
  14. e135ac5 Remove AMD special case for LAPIC based udelay() by Patrick Georgi · 12 years ago
  15. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  16. 2efc880 intel/gm45: new northbridge by Patrick Georgi · 12 years ago
  17. 3c84261 yabel: Use X86_* instead of the more verbose M.x86.REG_* by Patrick Georgi · 12 years ago
  18. 6446626 Use new system agent binaries by Stefan Reinauer · 12 years ago
  19. 313ec9d Sandybridge: Set PEG clock gating by Marc Jones · 12 years ago
  20. 7e8c8e9 Add PCIe init and NMode flag to PEI data structure by Stefan Reinauer · 12 years ago
  21. e8179b5 Add ddr3lv_support flag to pei_data structure by Duncan Laurie · 12 years ago
  22. 53508fe pei_data.h: Fix comment by Marc Jones · 12 years ago
  23. 48a4a7f Provide MRC with a console printing callback function by Vadim Bendebury · 12 years ago
  24. e5a0a5d Initial IGD OpRegion implementation by Stefan Reinauer · 12 years ago
  25. ad67791 Avoid using hardcoded values in MRC cache code by Vadim Bendebury · 12 years ago
  26. a1ea822 Make coreboot use the offset parameter in cbfstool create by Stefan Reinauer · 12 years ago
  27. 4c8027a Make register/value lists const by Stefan Reinauer · 12 years ago
  28. 357bb2d SandyBridge/IvyBridge: Use flash map to find MRC cache by Stefan Reinauer · 12 years ago
  29. c6b9f92 Add missing newline in error message by Stefan Reinauer · 12 years ago
  30. cf81b82 CMOS: Move MRC seed offset into upper bank by Duncan Laurie · 12 years ago
  31. 1e0ddf6 Fix some issues with new "reference" toolchain by Stefan Reinauer · 12 years ago
  32. 3e9155d northbridge/sch: move the \n so it reads a little better by Sebastian Andrzej Siewior · 12 years ago
  33. 59e3e02 northbridge/sch: read the size of main memory from the proper register by Sebastian Andrzej Siewior · 12 years ago
  34. 50dd47b northbridge/sch: Read the GPU memory from the correct PCI device by Sebastian Andrzej Siewior · 12 years ago
  35. 66fa9e2 northbridge/sch: don't overwrite hightables with GPU / TSEG memory by Sebastian Andrzej Siewior · 12 years ago
  36. 0279036 Remove chip.h files without config structure by Kyösti Mälkki · 12 years ago
  37. 72cee54 HAVE_HIGH_TABLES is gone by Patrick Georgi · 12 years ago
  38. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  39. 7874e9d Sandybridge: Fix integer overrun in romstage udelay() by Stefan Reinauer · 12 years ago
  40. cf8e466 Cleanup coreboot memory table includes by Kyösti Mälkki · 12 years ago
  41. 9ca1c0a Sandy/Ivy Bridge and Cougar/Panther Point: Fix names by Stefan Reinauer · 12 years ago
  42. 5e29f00 Intel and GFXUMA: drop redundant use of lb_add_memory_range() by Kyösti Mälkki · 12 years ago
  43. 7f189cc Intel Sandybridge and UMA: use mmio_resource() by Kyösti Mälkki · 12 years ago
  44. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 12 years ago
  45. d4ee808 sandybridge: reinitialize usbdebug after MRC by Sven Schnelle · 12 years ago
  46. 6ff1d36 Intel and GFXUMA: fix MTRR and use uma_resource() by Kyösti Mälkki · 12 years ago
  47. 08ef498 Intel 82810 and 82830: always room for PCI memory by Kyösti Mälkki · 12 years ago
  48. b5f5652 Intel i945 and sch: no memory over 4GB by Kyösti Mälkki · 12 years ago
  49. efff733 Refactor driver structs by Patrick Georgi · 12 years ago
  50. 1b3207e CTDP: Only do TDP down/nominal change from TNP0 by Duncan Laurie · 12 years ago
  51. 55864ef ACPI: Add support for runtime config TDP down by Duncan Laurie · 12 years ago
  52. f4d3623 ELOG: Add support for a monotonic boot counter in CMOS by Duncan Laurie · 12 years ago
  53. 696262b More descriptive error messages in Sandybridge raminit code by Stefan Reinauer · 12 years ago
  54. 9c4c6ab ELOG: Fix boot count increment for non-wake case by Duncan Laurie · 12 years ago
  55. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  56. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  57. b91a0f2 Rename cache_lbmem() to cache_ramstage() by Stefan Reinauer · 12 years ago
  58. 6097e19 Make ACPI code detect Sandy/Ivy Bridge dynamically by Stefan Reinauer · 12 years ago
  59. afcaac2 Drop (empty) sandybridge_late_initialization() by Stefan Reinauer · 12 years ago
  60. baae2d2 Add support for HM70 and NM70 LPC bridge by Stefan Reinauer · 12 years ago
  61. 542e962 Print PCI ID of PCH during boot up by Stefan Reinauer · 12 years ago
  62. c664387 Drop leading spaces from CPU name string by Stefan Reinauer · 12 years ago
  63. 4821489 Fix MRC cache update delays by Stefan Reinauer · 12 years ago
  64. 496f4a0 SandyBridge: Add another PCI device ID for northbridge by Walter Murphy · 12 years ago
  65. da83a5f Fixes to enable RC6 on IvyBridge by Duncan Laurie · 12 years ago
  66. ce6e9fe i945: Disable IGD if plugin VGA is preferred by Patrick Georgi · 12 years ago
  67. 8bacc40 Fix udelay() implementation for i945 romstage by Nico Huber · 12 years ago
  68. cda9f93 Intel SCH northbridge: fix resource index by Kyösti Mälkki · 12 years ago
  69. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  70. d422069 i5000: Fix resource allocation by Sven Schnelle · 12 years ago
  71. 34d86f0 i5000: reset system if raminit fails by Sven Schnelle · 12 years ago
  72. 7b48379 i5000: Add PCI ids for all i5000 flavours by Sven Schnelle · 12 years ago
  73. 6444bd4 i945: Reset IGD on boot by Patrick Georgi · 12 years ago
  74. 1454685 i5000: fix another typo by Sven Schnelle · 12 years ago
  75. 39b47d2 i5000: fix typos by Sven Schnelle · 12 years ago
  76. 1a7a7e6 i5000: enforce hard reset by Sven Schnelle · 12 years ago
  77. 88fc0b9 Sandybridge: Remove remnants of FDT support from MRC cache code by Stefan Reinauer · 12 years ago
  78. 6e901fd Sandybridge: Fix MRC cache calculation by Stefan Reinauer · 12 years ago
  79. bb11e60 Hook up MRC cache update by Stefan Reinauer · 12 years ago
  80. 1244f4b Rework Sandybridge MRC cache handling by Stefan Reinauer · 12 years ago
  81. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  82. f125d80 Add missing newline to printk in Sandybridge init code by Stefan Reinauer · 12 years ago
  83. adc05c1 Make Intel i5000 specific options only appear on i5000 systems by Stefan Reinauer · 12 years ago
  84. cafedcf Strip quotes from Sandybridge MRC blob by Stefan Reinauer · 12 years ago
  85. 7a3f36a Sandybridge: Display platform information early by Vadim Bendebury · 12 years ago
  86. 8508cff Update Ivybridge GT power meter tables by Duncan Laurie · 12 years ago
  87. dd585b8 Update ivybridge graphics initialization by Duncan Laurie · 12 years ago
  88. 7b508dd Only send ME Dram Init Done message on Sandybridge by Duncan Laurie · 12 years ago
  89. 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
  90. e6063fe Fix Sandybridge/Ivybridge mainboards according to code review by Stefan Reinauer · 12 years ago
  91. 6ea86b1 Sandybridge: Temporarily disable MRC cache finding code by Stefan Reinauer · 12 years ago
  92. e9dfdd9 Reverse Vendor ID & Device ID for map_oprom_vendev() by Martin Roth · 12 years ago
  93. 16401b8 SMM: Add udelay on Sandybridge systems by Stefan Reinauer · 12 years ago
  94. 93b4ed9 Intel e7505: build as separate object file by Kyösti Mälkki · 12 years ago
  95. 97c064f Intel e7505: enable ECC scrubbing by Kyösti Mälkki · 12 years ago
  96. 77e4f7d Intel e7505: refactor only by Kyösti Mälkki · 12 years ago
  97. 26c7b86 Intel e7505: handlers for undocumented registers by Kyösti Mälkki · 12 years ago
  98. 2c2e78d Unify IO APIC address specification by Patrick Georgi · 13 years ago
  99. 5c1ff92 Intel e7505: cleanups by Kyösti Mälkki · 12 years ago
  100. 5bd271b Intel e7505: renames only by Kyösti Mälkki · 12 years ago