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review.coreboot.org / coreboot / 7686a56574a6773717b49a51786f301970d1c69c / src / southbridge / intel / bd82x6x / pch.h
  1. 7686a56 sandy/ivybridge: Native raminit. by Vladimir Serbinenko · 10 years ago
  2. 9c50e6a Intel BD82x6x: LPC: Unify I/O APIC setup by Paul Menzel · 11 years ago
  3. 3f5f6d8 Drop prototype guarding for romcc by Stefan Reinauer · 11 years ago
  4. 783f226 Add bd82x6x PCH functions to SMM by Marc Jones · 11 years ago
  5. e7ae96f Add Intel Panther Point USB3 initialization by Marc Jones · 12 years ago
  6. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  7. d4bc067 SPI: Add early romstage SPI driver using hardware sequencing by Duncan Laurie · 12 years ago
  8. 924342b SPI: Add Fast Read to the OPMENU for locked down SPI by Duncan Laurie · 12 years ago
  9. 9d81c19 PCH: Add register descriptions used by IGD OpRegion by Stefan Reinauer · 12 years ago
  10. 9aeb694 hpet: common ACPI generation by Patrick Georgi · 12 years ago
  11. 16b022a Perform additional programming requirements for SATA by Stefan Reinauer · 12 years ago
  12. cfb64bd SATA: Add option to configure gen3 transmitter by Duncan Laurie · 12 years ago
  13. 800e950 ELOG: Log boot-time events found in southbridge by Duncan Laurie · 12 years ago
  14. 22935e1 CPU: Set flex ratio to nominal TDP ratio in bootblock by Duncan Laurie · 12 years ago
  15. b9fe01c Add an option to enable PCIe root port coalescing by Duncan Laurie · 12 years ago
  16. 8e07382 Add support for Intel Panther Point PCH by Stefan Reinauer · 12 years ago