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review.coreboot.org / coreboot / 730a043fb6cb4dd3cb5af8f8640365727b598648 / src / northbridge / amd / amdmct / mct_ddr3 / mct_d.c
  1. 730a043 cpu/amd: Add initial AMD Family 15h support by Timothy Pearson · 9 years ago
  2. 2a83935 northbridge/amd/amdfam10: Set DIMM voltage based on SPD data by Timothy Pearson · 9 years ago
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. 59d0e04 northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) support by Timothy Pearson · 9 years ago
  5. b8a355d northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization by Timothy Pearson · 9 years ago
  6. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  7. 620fa5f northbridge/amd/amdfam10: Collect DIMM information for ramstage use by Timothy Pearson · 9 years ago
  8. 0f92f63 Uniformly spell frequency unit symbol as Hz by Elyes HAOUAS · 10 years ago
  9. ba363d3 northbridge/amd/amdmct: Superfluous parenthesis in if-statements by Edward O'Callaghan · 10 years ago
  10. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  11. 067d223 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. by Marc Jones · 12 years ago
  12. 328a694 AMD CPU and chipset fixes for compilation with gcc 4.6 by Stefan Reinauer · 13 years ago
  13. 471f103 This patch sets max freq defaults for ddr2 and ddr3for fam10. by Marc Jones · 13 years ago
  14. 69436e1 Fix some settings fo AMD MCT. It is based on BIOS test suite. by Zheng Bao · 14 years ago
  15. c3af12f Trivial. Spell checking. by Zheng Bao · 14 years ago
  16. 7b1a3c3 Trivial. re-Indent the code. by Zheng Bao · 14 years ago
  17. 7cdf1ec Obviously missing brackets. by Xavi Drudis Ferran · 14 years ago
  18. 951a0fe Fix the typo. Field DisAutoRefresh is in DramTimngHi. by Zheng Bao · 14 years ago
  19. e150e9a Also improve boot time on AMD for the DDR3 code path. Fix a typo, too. by Arne Georg Gleditsch · 14 years ago
  20. f7a999a Trivial. Currently the max frequency is preset as 400Mhz. We need to set a by Zheng Bao · 14 years ago
  21. 08c92e0 AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. by Kerry She · 14 years ago
  22. 9fae99f Get Byte65/66 for register manufacture ID code. RegMan1Present will by Zheng Bao · 14 years ago
  23. 108d30b Trivial syntax correction of AMD mct_ddr3 dir. by Kerry She · 14 years ago
  24. eb75f65 DDR3 support for AMD Fam10. by Zheng Bao · 14 years ago