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review.coreboot.org / coreboot / 730a043fb6cb4dd3cb5af8f8640365727b598648 / src / northbridge / amd / amdmct / mct / mct_d.c
  1. 730a043 cpu/amd: Add initial AMD Family 15h support by Timothy Pearson · 9 years ago
  2. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  3. b8a355d northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization by Timothy Pearson · 9 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 620fa5f northbridge/amd/amdfam10: Collect DIMM information for ramstage use by Timothy Pearson · 9 years ago
  6. b6fa61a northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later by Timothy Pearson · 9 years ago
  7. 65b72ab northbridge: Drop print_ implementation from non-romcc boards by Stefan Reinauer · 10 years ago
  8. 0f92f63 Uniformly spell frequency unit symbol as Hz by Elyes HAOUAS · 10 years ago
  9. ba363d3 northbridge/amd/amdmct: Superfluous parenthesis in if-statements by Edward O'Callaghan · 10 years ago
  10. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  11. 067d223 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. by Marc Jones · 12 years ago
  12. 2ca2f17 Add AMD C32 support. It is based on other existing Fam10 code. by Zheng Bao · 13 years ago
  13. 69436e1 Fix some settings fo AMD MCT. It is based on BIOS test suite. by Zheng Bao · 14 years ago
  14. c3af12f Trivial. Spell checking. by Zheng Bao · 14 years ago
  15. 7b1a3c3 Trivial. re-Indent the code. by Zheng Bao · 14 years ago
  16. 7cdf1ec Obviously missing brackets. by Xavi Drudis Ferran · 14 years ago
  17. 0c51ddd Complete the code which was missing. by Zheng Bao · 14 years ago
  18. d6689ed Please find appended. This patch gets rid of the %gs magic altogether, by Arne Georg Gleditsch · 14 years ago
  19. e150e9a Also improve boot time on AMD for the DDR3 code path. Fix a typo, too. by Arne Georg Gleditsch · 14 years ago
  20. 6556534 Apparently, it's not crucial to clear this at the exact moment we switch by Arne Georg Gleditsch · 14 years ago
  21. 08c92e0 AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. by Kerry She · 14 years ago
  22. ad894c5 Get rid of a few more warnings. by Myles Watson · 14 years ago
  23. 14e2277 Since some people disapprove of white space cleanups mixed in regular commits by Stefan Reinauer · 14 years ago
  24. d653211 zero warnings days: unify mp tables. fix warnings. by Stefan Reinauer · 14 years ago
  25. 075fbe8 Remove a few more warnings from fam10. by Myles Watson · 14 years ago
  26. c02b4fc printk_foo -> printk(BIOS_FOO, ...) by Stefan Reinauer · 14 years ago
  27. fd9c9b8 Use the coreboot pci config read/write functions instead of direct cf8/cfc by Marc Jones · 15 years ago
  28. 1476a9e Without this patch, if we only got a DIMM in Channel B, memory can not be by Zheng Bao · 15 years ago
  29. a774192 Fix for Erratum 350 for AMD Fam10h CPUs. by Marco Schmidt · 15 years ago
  30. ce00f1d Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de> by Stefan Reinauer · 16 years ago
  31. c3ec1ac Memory initialization support for AMD Fam10 B3 (B0-B2 already supported). by Marc Jones · 16 years ago
  32. e3aeb93 Bring Fam10 memory controller init up to date with the latest AMD BKDG by Marc Jones (marc.jones · 16 years ago
  33. 7e61e45 Please bear with me - another rename checkin. This qualifies as trivial, no by Stefan Reinauer · 17 years ago
  34. 8ae8c88 Initial AMD Barcelona support for rev Bx. by Marc Jones · 17 years ago