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review.coreboot.org / coreboot / 6c1e81059dc928df6546289073ae61939b52b196 / src / soc / imgtec / pistachio / romstage.c
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 8 years ago
  2. 1d4c305 pistachio: sort included header files by Ionela Voinescu · 8 years ago
  3. 11f33e4 pistachio: initialize cbmem area to be empty by Ionela Voinescu · 8 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 8 years ago
  5. d6aaca9 pistachio: add DDR2 initialization code by Ionela Voinescu · 8 years ago
  6. 8880df1 pistachio: don't open code ramstage loading by Aaron Durbin · 8 years ago
  7. 2d510d0 urara: use proper SOC name by Vadim Bendebury · 9 years ago[Renamed from src/soc/imgtec/danube/romstage.c]
  8. c7b3f72 danube: use SOC specific rom stage code by Vadim Bendebury · 9 years ago