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review.coreboot.org / coreboot / 6c191d8af41859dd94a01c6a868a9186d0120923 / src / soc / intel / quark / chip.c
  1. 6c191d8 romstage_handoff: add helper to determine resume status by Aaron Durbin · 8 years ago
  2. c6ec8dd fsp2_0: implement stage cache for silicon init by Brandon Breitenstein · 8 years ago
  3. f74ce24 soc/intel/quark: Clean up debug output levels by Lee Leahy · 8 years ago
  4. 01728bb soc/intel/quark: Prepare for FSP2.0 support by Lee Leahy · 8 years ago
  5. 14d0926 soc/intel/quark: Remove use of EDK-II macros and data types by Lee Leahy · 8 years ago
  6. 63e3dff soc/intel/quark: Add temperature sensor support by Lee Leahy · 8 years ago
  7. eee0e229 soc/intel/quark: Remove UPD parameters by Lee Leahy · 8 years ago
  8. e99e2b6 soc/intel/quark: Add the UPD support for SiliconInit by Lee Leahy · 9 years ago
  9. 535333d soc/intel/quark: Establish the Memory Map by Lee Leahy · 9 years ago
  10. b457649 soc/intel/quark: Enumerate the PCI devices by Lee Leahy · 9 years ago
  11. d4edacb soc/intel/quark: Call FSP SiliconInit by Lee Leahy · 9 years ago