1. 6bedbd6 soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD by Furquan Shaikh · 3 years, 4 months ago
  2. 1e67f07 siemens/mc_apl1: Activate clock spreading for PTN3460 by Mario Scheithauer · 3 years, 4 months ago
  3. 66038c8 siemens/mc_apl1: Add new mainboard variant mc_apl2 by Mario Scheithauer · 3 years, 4 months ago
  4. 7e15e87 siemens/mc_apl1: Make the DDR memory swizzle data configurable by Mario Scheithauer · 3 years, 4 months ago
  5. e27c096 siemens/mc_apl1: Correct the Tx signal from SATA interface by Mario Scheithauer · 3 years, 5 months ago
  6. 403458e siemens/mc_apl1: Extend circuit life by clock gating and power gating by Mario Scheithauer · 3 years, 5 months ago
  7. 5650896 siemens/mc_apl1: Disable PCI clock outputs on XIO bridge by Mario Scheithauer · 3 years, 5 months ago
  8. 16ebc98 siemens/mc_apl1: Select DDR50 mode for eMMC by Mario Scheithauer · 3 years, 5 months ago
  9. 0e1a526 siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard by Mario Scheithauer · 3 years, 5 months ago
  10. 053851f siemens/mc_apl1: Move board specific things to mc_apl1 variant by Mario Scheithauer · 3 years, 5 months ago
  11. c4986eb soc/intel/common/block: Add common chip config block by Subrata Banik · 3 years, 9 months ago
  12. 6141353 siemens/mc_apl1: Move board specific things to mc_apl1 variant by Mario Scheithauer · 3 years, 9 months ago
  13. d127be1 siemens/mc_apl1: Provide baseboard and variant concepts by Mario Scheithauer · 3 years, 9 months ago