Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
6935350ad6610fca943afc4ae96125760538f98c
/
src
/
soc
/
intel
/
alderlake
/
fsp_params.c
6935350
soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC
by Maulik V Vaghela
· 3 years, 4 months ago
bc1941f
soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry
by Cliff Huang
· 3 years, 6 months ago
812b54e
soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selected
by Ronak Kanabar
· 3 years, 6 months ago
5b302b2
soc/intel/alderlake: Refactor PCIE port config
by Eric Lai
· 3 years, 9 months ago
85144d9
soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
by Subrata Banik
· 3 years, 7 months ago
99289a8
soc/intel/alderlake: Update CPU microcode patch base address/size
by Subrata Banik
· 3 years, 8 months ago
2871e0e
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
by Subrata Banik
· 3 years, 11 months ago