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review.coreboot.org / coreboot / 67031a565b3179fa5a28282fc2e24b47d16003e8 / src / cpu / intel / model_206ax / model_206ax.h
  1. 67031a5 cpu/intel/sandybridge: Put stage cache into TSEG by Arthur Heymans · 7 years ago
  2. 7b5f12b9 cpu/intel: Indent with tabs by Lee Leahy · 7 years ago
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. a3e41c0 Migrate 206ax to SMM_MODULES by Vladimir Serbinenko · 9 years ago
  5. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  6. 3f5f6d8 Drop prototype guarding for romcc by Stefan Reinauer · 11 years ago
  7. 644e83b speedstep: Deduplicate some MSR identifiers by Patrick Georgi · 12 years ago
  8. 5563211 CPU: Add option to set TCC activation offset by Duncan Laurie · 12 years ago
  9. c0f2cfb Fix comment to reference IvyBridge, too by Stefan Reinauer · 12 years ago
  10. 22935e1 CPU: Set flex ratio to nominal TDP ratio in bootblock by Duncan Laurie · 12 years ago
  11. 4e4320f CPU: Update ivybridge PP1 current limit value by Duncan Laurie · 12 years ago
  12. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  13. 5c55463 Add support for Intel Sandybridge CPU by Stefan Reinauer · 12 years ago