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review.coreboot.org / coreboot / 66b0d55d326540e400ad3fa5130666dbd03b9694 / src / soc / intel / sch / smihandler.c
  1. d45114f intel PCI ops: Remove explicit PCI MMCONF access by Kyösti Mälkki · 11 years ago
  2. 4bab6e7 intel/sch: Merge northbridge and southbridge in src/soc by Stefan Reinauer · 8 years ago[Renamed from src/southbridge/intel/sch/smihandler.c]
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 182e551f smihandler.c: Fix doxygen errors in southbridge_smi_handler by Martin Roth · 10 years ago
  6. 54d6abd Drop some duplicates of PCI-e config functions by Kyösti Mälkki · 11 years ago
  7. 62f8083 Fix cycle error in intel southbridges to display GPI status by Konstantin Aladyshev · 11 years ago
  8. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  9. f4dc1a7 SMM: add defines for APM_CNT register by Sven Schnelle · 13 years ago
  10. be61a17 Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board which uses it. by Patrick Georgi · 14 years ago