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review.coreboot.org / coreboot / 62f788e24469c0e12dbf427594cc8150ffa4336f / src / arch / riscv / romstage.c
  1. d30d9a2 src: Remove redundant include <rules.h> by Elyes HAOUAS · 3 years, 6 months ago
  2. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  3. d1e50f9 src/arch/riscv: Convert to SPDX license header by Patrick Georgi · 4 years, 6 months ago
  4. c01d092 arch/riscv: Rename `stages.c` to `romstage.c` by Nico Huber · 4 years, 10 months ago[Renamed (73%) from src/arch/riscv/stages.c]
  5. 1a64194 riscv: Remove unused headers by Patrick Rudolph · 5 years ago
  6. 820dcfc riscv: Simplify payload handling by Xiang Wang · 6 years ago
  7. 5c29daa buildsystem: Promote rules.h to default include by Kyösti Mälkki · 8 years ago
  8. 26f725e riscv: add support to block smp in each stage by Xiang Wang · 6 years ago
  9. 042a833 arch/riscv: Pass the bootrom-provided FDT to the payload by Jonathan Neuschäfer · 7 years ago
  10. ae3f302 arch: remove stage_exit() by Aaron Durbin · 9 years ago
  11. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  12. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  13. e0e784a Add UCB RISCV support for architecture, soc, and emulation mainboard.. by Ronald G. Minnich · 10 years ago