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review.coreboot.org / coreboot / 600fa266bdc8740126420e63579a5b9d103ca960 / src / mainboard / google / beltino / devicetree.cb
  1. 600fa26 nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree by Arthur Heymans · 1 year, 8 months ago
  2. af4bd56 sb/intel: Use `bool` for PCIe coalescing option by Angel Pons · 2 years, 7 months ago
  3. ba5761a cpu/intel/haswell: Factor out ACPI C-state values by Angel Pons · 3 years, 9 months ago
  4. 8084b38 sb/intel/lynxpoint/sata: Always use AHCI mode by Angel Pons · 3 years, 9 months ago
  5. 9f78127 lynxpoint: Factor out PIRQ routing from devicetree by Angel Pons · 4 years ago
  6. 4276050 mb/*/*/devicetree.cb: Normalize disabled PIRQ values by Angel Pons · 4 years ago
  7. 8aab787 haswell: Move some MRC settings to devicetree by Angel Pons · 4 years ago
  8. a0259b4 mb/google/{beltino,jecht}: Drop SIO configuration lines by Nico Huber · 4 years, 7 months ago
  9. 3044af7 mb/google,samsung/*: Add LPC TPM chip driver to devicetree by Matt DeVillier · 6 years ago
  10. 81ae67a Add Haswell Chromeboxes/Chromebase using variant board scheme by Matt DeVillier · 8 years ago