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5b302b2ed213b8cfbeb901aaed650bf73c3742fc
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src
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soc
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intel
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alderlake
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fsp_params.c
5b302b2
soc/intel/alderlake: Refactor PCIE port config
by Eric Lai
· 3 years, 9 months ago
85144d9
soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
by Subrata Banik
· 3 years, 7 months ago
99289a8
soc/intel/alderlake: Update CPU microcode patch base address/size
by Subrata Banik
· 3 years, 8 months ago
2871e0e
soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
by Subrata Banik
· 3 years, 11 months ago