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review.coreboot.org / coreboot / 593e7de5a777db0310da7221f81982b6b3ed4929 / src / northbridge / intel / sandybridge / northbridge.c
  1. 593e7de nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge by Nico Huber · 9 years ago
  2. 9d9ce0d nb/intel/sandybridge: Add ACPI DMAR table by Nico Huber · 9 years ago
  3. bb9469c nb/intel/sandybridge: Enable basic IOMMU support by Nico Huber · 9 years ago
  4. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  5. 3660c0f northbridge/intel/sandybridge: Enable PEG clock-gating on demand by Patrick Rudolph · 9 years ago
  6. c16e9dfa Create i945-ivy smm tseg init based on ivy code. by Vladimir Serbinenko · 9 years ago
  7. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  8. 9f74462 northbridge/intel: Use DEVICE_NOOP macro over dummy symbol by Edward O'Callaghan · 10 years ago
  9. 3517038 intel/sandybridge: Add PCI ID for northbridge 0x150 by Damien Zammit · 10 years ago
  10. 0a66991 acpi: Remove explicit pointer tracking in per-device ssdt. by Vladimir Serbinenko · 10 years ago
  11. 35c0f43 Move nehalem/sandy/ivy to per-device acpi by Vladimir Serbinenko · 10 years ago
  12. c862e44 northbridge/intel: Drop use of set_top_of_ram() by Kyösti Mälkki · 10 years ago
  13. f7bfc34 intel: Remove GFXUMA and related global variables by Kyösti Mälkki · 11 years ago
  14. a6130fc intel: Drop obsolete comments on MTRR usage by Kyösti Mälkki · 10 years ago
  15. 4337020 Remove CACHE_ROM. by Vladimir Serbinenko · 10 years ago
  16. cb08e16 CBMEM intel: Define get_top_of_ram() once per chipset by Kyösti Mälkki · 11 years ago
  17. f9f74af CBMEM x86: Unify get_cbmem_toc() by Kyösti Mälkki · 11 years ago
  18. dcb688e CBMEM: Unify get_top_of_ram() by Kyösti Mälkki · 11 years ago
  19. 42f4651 CBMEM northbridges: Remove references to global high_tables_base by Kyösti Mälkki · 11 years ago
  20. 872c922 Fix MMCONF_SUPPORT_DEFAULT for ramstage by Kyösti Mälkki · 11 years ago
  21. eac00d2 intel/sandybridge: Locate CBMEM TOC early in ramstage by Kyösti Mälkki · 11 years ago
  22. 243aa44 boot: remove cbmem_post_handling() by Aaron Durbin · 11 years ago
  23. c6f2722 sandybridge: enable ROM caching by Aaron Durbin · 11 years ago
  24. c965076 resources: introduce reserved_ram_resource() by Aaron Durbin · 11 years ago
  25. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  26. fd611f9 Drop CONFIG_WRITE_HIGH_TABLES by Stefan Reinauer · 11 years ago
  27. 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster by Stefan Reinauer · 11 years ago
  28. 4aff445 sconfig: rename pci_domain -> domain by Stefan Reinauer · 11 years ago
  29. 5079a0d Remove assembly coded log2 function by Ronald G. Minnich · 12 years ago
  30. cf8e466 Cleanup coreboot memory table includes by Kyösti Mälkki · 12 years ago
  31. 9ca1c0a Sandy/Ivy Bridge and Cougar/Panther Point: Fix names by Stefan Reinauer · 12 years ago
  32. 5e29f00 Intel and GFXUMA: drop redundant use of lb_add_memory_range() by Kyösti Mälkki · 12 years ago
  33. 7f189cc Intel Sandybridge and UMA: use mmio_resource() by Kyösti Mälkki · 12 years ago
  34. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 12 years ago
  35. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  36. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  37. 496f4a0 SandyBridge: Add another PCI device ID for northbridge by Walter Murphy · 12 years ago
  38. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  39. bb11e60 Hook up MRC cache update by Stefan Reinauer · 12 years ago
  40. 1244f4b Rework Sandybridge MRC cache handling by Stefan Reinauer · 12 years ago
  41. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  42. 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
  43. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago