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review.coreboot.org / coreboot / 58f73a69cd83c46604795d728f296779c1de162c / src / cpu / intel
  1. 58f73a6 build: separate CPPFLAGS from CFLAGS by Patrick Georgi · 8 years ago
  2. 98f49d2 build: CPPFLAGS is more common than INCLUDES by Patrick Georgi · 8 years ago
  3. 3d68b1a cpu/intel: Add CPU socket rPGA988B by Zaolin · 8 years ago
  4. 5c3f384 Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT by Kyösti Mälkki · 8 years ago
  5. 2dd3f87 cougar_canyon2: Switch CPU/NB/SB to the shared FSP code by Martin Roth · 8 years ago
  6. 99ac98f Introduce stage-specific architecture for coreboot by Furquan Shaikh · 8 years ago
  7. 014baea haswell: move to mp_init library by Aaron Durbin · 8 years ago
  8. fd33781 Move ARCH_* from board/Kconfig to cpu or soc Kconfig. by Furquan Shaikh · 8 years ago
  9. 20f25dd Rename coreboot_ram stage to ramstage by Furquan Shaikh · 8 years ago
  10. 8171496 Get rid of HAVE_INIT_TIMER config option by Furquan Shaikh · 8 years ago
  11. 3eb8eb7 rmodules: use rmodtool to create rmodules by Aaron Durbin · 8 years ago
  12. 5809a73 Make POST device configurable. by Idwer Vollering · 8 years ago
  13. 4337020 Remove CACHE_ROM. by Vladimir Serbinenko · 9 years ago
  14. 10b3974 intel/model_2065x: Fix APICID generation. by Vladimir Serbinenko · 8 years ago
  15. 6a36004 haswell: backup the default SMM region on resume by Aaron Durbin · 8 years ago
  16. 0f33307 coreboot: infrastructure for different ramstage loaders by Aaron Durbin · 9 years ago
  17. 2c78726 PCI: Drop includes under cpu by Kyösti Mälkki · 8 years ago
  18. 9db1c4e usbdebug: Drop obsolete code by Kyösti Mälkki · 9 years ago
  19. 5ef4220 cpu/intel/model_2065x: Add model 20652 by Vladimir Serbinenko · 9 years ago
  20. ba6b07e cpu/intel: allow non-packaged scoped turbo setting by Aaron Durbin · 9 years ago
  21. 75e2974 coreboot: config to cache ramstage outside CBMEM by Aaron Durbin · 9 years ago
  22. d37705c vboot: provide empty vboot_verify_firmware() by Aaron Durbin · 9 years ago
  23. e676767 intel: fix microcode compilation failure in bootblock by Aaron Durbin · 9 years ago
  24. 4fe9813 src/cpu: Fix spelling of MTTR to MTRR by Paul Menzel · 9 years ago
  25. 9c70adf intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH. by Vladimir Serbinenko · 9 years ago
  26. 07d881a0 cpu/intel: Remove dummy terminators from microcode blobs by Alexandru Gagniuc · 9 years ago
  27. 2c38f50 cpu/intel: Make all Intel CPUs load microcode from CBFS by Alexandru Gagniuc · 9 years ago
  28. bbf013c nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash by Kyösti Mälkki · 9 years ago
  29. 107f72e Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR by Kyösti Mälkki · 9 years ago
  30. 5d1ada0 intel/fsp: Fix microcode including by Patrick Georgi · 9 years ago
  31. 68a8431 haswell: Update microcode revision by Duncan Laurie · 9 years ago
  32. b1ae030 cpu/intel: Do not rely on CBFS microcode having a terminator by Alexandru Gagniuc · 9 years ago
  33. 66e0c4c cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS by Alexandru Gagniuc · 9 years ago
  34. 118d105 haswell: Export functions for CPU family+model and stepping by Duncan Laurie · 9 years ago
  35. 768903e haswell: Update ULT microcode to rev 14h by Duncan Laurie · 9 years ago
  36. 16cbf89 haswell: VR controller configuration by Aaron Durbin · 9 years ago
  37. c70353f haswell: Misc power management setup and fixes by Duncan Laurie · 9 years ago
  38. f589909 cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig option by Alexandru Gagniuc · 9 years ago
  39. bdafcfa Add the Intel FSP 206ax CPU core support by Marc Jones · 9 years ago
  40. c7633f4 slippy/falco/peppy: Fix SPD GPIO initialization. by Aaron Durbin · 9 years ago
  41. 5afca13 haswell: check for clean reset by Aaron Durbin · 9 years ago
  42. fd0bc14 haswell: Update ULT microcode to 0x10 by Duncan Laurie · 9 years ago
  43. 1c09710 haswell: Remove limit on package C-state by Duncan Laurie · 9 years ago
  44. 5b41785 haswell: split microcode between ULT and non-ULT by Aaron Durbin · 9 years ago
  45. 3e996a5 haswell: Update ULT microcode to rev 'a' by Duncan Laurie · 9 years ago
  46. e1e87e0 haswell: Configure PCH power sharing for ULT by Duncan Laurie · 9 years ago
  47. f24262d haswell: calibrate 24MHz clock against BCLK by Aaron Durbin · 9 years ago
  48. 7c35131 haswell: configure c-states by Aaron Durbin · 9 years ago
  49. 25b8b7b haswell: Put each logical processor in its own P-state domain by Duncan Laurie · 9 years ago
  50. 77647b3 haswell: Update microcode for ULT/40651 to rev 8 by Duncan Laurie · 9 years ago
  51. 71f35eb Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x. by Vladimir Serbinenko · 9 years ago
  52. 75b90a1 Remove MRC variables from 2065x CAR init. by Vladimir Serbinenko · 9 years ago
  53. fe6bdd9 Fix error message on wrong compiles of 2065x by Vladimir Serbinenko · 9 years ago
  54. d8cfd23 intel/2065x: Use TSC for udelay() by Vladimir Serbinenko · 9 years ago
  55. cbf5bdf CBMEM: Always select CAR_MIGRATION by Kyösti Mälkki · 9 years ago
  56. 3d45c40 timestamps: Stash early timestamps in CAR_GLOBAL by Kyösti Mälkki · 9 years ago
  57. e28bd4a timestamps intel: Move timestamp scratchpad to chipset by Kyösti Mälkki · 9 years ago
  58. 8eaf1e7 cpu/intel/model_67x: Add missing include by Kyösti Mälkki · 9 years ago
  59. 4c3ab73 cpu: Fix spelling by Martin Roth · 9 years ago
  60. 2c516ed usbdebug: Drop old includes by Kyösti Mälkki · 9 years ago
  61. 8ee04d7 usbdebug: Put ehci_debug_info in CAR_GLOBAL by Kyösti Mälkki · 9 years ago
  62. 7cced0d ec: Add romstage function for checking and rebooting EC by Duncan Laurie · 9 years ago
  63. e49679d usbdebug: Drop temporary disables of log output by Kyösti Mälkki · 9 years ago
  64. 22dcdd9 Add support for Intel Nehalem CPU by Vladimir Serbinenko · 9 years ago
  65. 66da043 haswell: allow for disabled hyperthreading by Aaron Durbin · 9 years ago
  66. 4e01cfb cpu/intel/haswell/Kconfig: Intend help text with two spaces by Paul Menzel · 9 years ago
  67. 5b54d35 haswell: enable cache-as-ram migration by Aaron Durbin · 9 years ago
  68. 38c326d x86: add thread support by Aaron Durbin · 9 years ago
  69. 3f5f6d8 Drop prototype guarding for romcc by Stefan Reinauer · 9 years ago
  70. 648d166 copy_and_run: drop boot_complete parameter by Stefan Reinauer · 9 years ago
  71. 39ecc65 haswell: use asmlinkage for assembly-called funcs by Aaron Durbin · 9 years ago
  72. 7cb1ba9 haswell: use tsc for udelay() by Aaron Durbin · 9 years ago
  73. c46cc6f haswell: 24MHz monotonic time implementation by Aaron Durbin · 9 years ago
  74. 2c88cc0 Intel microcode: Return when `microcode_updates` is `NULL` by Vladimir Serbinenko · 9 years ago
  75. 23f5016 haswell: enable ROM caching by Aaron Durbin · 9 years ago
  76. 13cc952 haswell: keep ROM cache enabled by Aaron Durbin · 9 years ago
  77. 0f0fe10 haswell: use new interface to disable rom caching by Aaron Durbin · 9 years ago
  78. af3158c lynxpoint: split clearing and enabling of smm by Aaron Durbin · 9 years ago
  79. 8dddc30 haswell: Add microcode for ULT C0 stepping 0x40651 by Duncan Laurie · 9 years ago
  80. d02bb62 haswell: vboot path support in romstage by Aaron Durbin · 9 years ago
  81. c0cbd6e haswell: use dynamic cbmem by Aaron Durbin · 9 years ago
  82. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 9 years ago
  83. 71c7cdc Intel: Update CPU microcode for 6fx CPUs by Stefan Reinauer · 9 years ago
  84. b70197b Intel: Update CPU microcode for 106cx CPUs by Stefan Reinauer · 9 years ago
  85. b631f9c Intel: Update CPU microcode script by Stefan Reinauer · 9 years ago
  86. 1ad5564 lynxpoint: Add helper functions for reading PM and GPIO base by Duncan Laurie · 9 years ago
  87. b86113f haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option by Aaron Durbin · 9 years ago
  88. f7cdfe5 haswell: implement ramstage caching in SMM region by Aaron Durbin · 9 years ago
  89. 8ce667e haswell: add multipurpose SMM memory region by Aaron Durbin · 9 years ago
  90. 67481dd haswell: set TSEG as WB cacheable in romstage by Aaron Durbin · 9 years ago
  91. 738af67 haswell: support for parallel SMM relocation by Aaron Durbin · 9 years ago
  92. bf396ff haswell: use s3_resume field in romstage_handoff by Aaron Durbin · 9 years ago
  93. ef4275b x86: protect against abi assumptions from compiler by Aaron Durbin · 10 years ago
  94. e2d9e5b haswell: support for CONFIG_RELOCATABLE_RAMSTAGE by Aaron Durbin · 10 years ago
  95. a146d58 ramstage: prepare for relocation by Aaron Durbin · 10 years ago
  96. 2c3f161 Intel: Update CPU microcode for Sandybridge/Ivybridge CPUs by Stefan Reinauer · 9 years ago
  97. 511c4b7 Intel: Update CPU microcode for 1067x CPUs by Stefan Reinauer · 9 years ago
  98. 8c20399 haswell: wait 10ms after INIT IPI by Aaron Durbin · 10 years ago
  99. 305b1f0 haswell: Parallel AP bringup by Aaron Durbin · 10 years ago
  100. 98ffb42 intel microcode: split up microcode loading stages by Aaron Durbin · 10 years ago