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review.coreboot.org / coreboot / 555c9b6268febf001e887fbb9e3c3f0901a371ac / src / mainboard / intel / tglrvp / romstage_fsp_params.c
  1. 555c9b6 soc/intel/tigerlake: Remove Jasper Lake SoC references by Aamir Bohra · 4 years, 5 months ago
  2. 078bc41 mainboard/[g-p]*: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  3. 9900cf8 mb/intel/tglrvp: Add memory config for Tiger Lake UP4 by Srinidhi N Kaushik · 4 years, 5 months ago
  4. fdba0cd mb/intel/tglrvp: add Tiger Lake memory initialization support by Srinidhi N Kaushik · 4 years, 6 months ago
  5. ebb2d3c mb/intel/tglrvp: Add initial mainboard code by Ravi Sarawadi · 4 years, 8 months ago