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review.coreboot.org / coreboot / 4946804f0b6536df3e7a46654c0dbbc3172b1de8 / src / mainboard / siemens / mc_apl1 / variants / mc_apl3 / mainboard.c
  1. 4946804 siemens/mc_apl3: Disable PCI clock outputs on XIO bridges by Mario Scheithauer · 6 years ago
  2. 04ea73e siemens/mc_apl3: Set Full Reset Bit into Reset Control Register by Mario Scheithauer · 6 years ago
  3. d985cdc siemens/mc_apl3: Set bus master bit for on-board PCI device by Mario Scheithauer · 6 years ago
  4. bcbcecd siemens/mc_apl3: Remove the correction of the Tx signal for SATA by Mario Scheithauer · 6 years ago
  5. 98689df siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices by Mario Scheithauer · 6 years ago
  6. 58bf3e7 siemens/mc_apl3: Add new mainboard variant mc_apl3 by Mario Scheithauer · 6 years ago