1. 49111cd soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table by John Zhao · 1 year, 11 months ago
  2. 18129f9 soc/intel/tigerlake: Enable HDA through dev_enabled by Srinidhi N Kaushik · 1 year, 9 months ago
  3. 528ae9e soc/tigerlake: Correct FSP log interface by Wonkyu Kim · 1 year, 9 months ago
  4. 56626cf soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig by Subrata Banik · 1 year, 9 months ago
  5. dba6c4c soc/intel/tigerlake: Update FSP params for Jasper Lake by Maulik V Vaghela · 1 year, 11 months ago
  6. 2f2c7eb soc/intel/tigerlake: Enable Audio on TGL by Srinidhi N Kaushik · 1 year, 11 months ago
  7. 1ab6f0c soc/intel/tigerlake: Configure TCSS xHCI and xDCI by Wonkyu Kim · 1 year, 10 months ago
  8. c332a47 soc/intel/tigerlake: Disable image clocks by Wonkyu Kim · 1 year, 10 months ago
  9. 9f2e3ad soc/intel/tigerlake: Enable DP ports according to board design by Wonkyu Kim · 1 year, 10 months ago
  10. 591b0ff soc/intel/tigerlake: Configure ClkReq according to mainboard design by Wonkyu Kim · 1 year, 11 months ago
  11. d801b1f soc/intel/tigerlake: Update fsp_params for TGL by Srinidhi N Kaushik · 2 years ago
  12. 50ee91c soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig by Maulik V Vaghela · 2 years ago[Copied from src/soc/intel/tigerlake/romstage/fsp_params.c]
  13. baf6d6e soc/intel/tigerlake/romstage: Do initial SoC commit till romstage by Subrata Banik · 2 years, 1 month ago