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review.coreboot.org / coreboot / 48c389e69ebb3922594ccdd4664e7645d399920a / src / southbridge / intel / lynxpoint / pcie.c
  1. 48c389e PCI ops: Define read-modify-write routines globally by Kyösti Mälkki · 11 years ago
  2. 273a8dc southbridge/intel/lynxpoint: Use common gpio.c by Patrick Rudolph · 9 years ago
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 3106d0f haswell: Misc updates from 1.6.1 ref code by Duncan Laurie · 11 years ago
  6. 249a03b lynxpoint: Add devicetree config option to force enable ASPM by Duncan Laurie · 11 years ago
  7. 1c4289d lynxpoint: enable clock gating by Aaron Durbin · 11 years ago
  8. ab365af lynxpoint: implement additional programming steps by Stefan Reinauer · 11 years ago
  9. c0254e6 lynxpoint: disable pcie devices based on config by Aaron Durbin · 11 years ago
  10. 60f8208 lynxpoint: move all pcie device handling to pcie.c by Aaron Durbin · 11 years ago
  11. 386b3e6 intel/lynxpoint: remove explicit pcie config accesses by Kyösti Mälkki · 11 years ago
  12. 74c0d05 lynxpoint: Update device IDs and clock gating setup by Duncan Laurie · 12 years ago
  13. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago