Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 4565aea8fbb114f65ecce7bdaaa538f80c382599 / src / southbridge / amd / pi / hudson / lpc.c
  1. 4565aea southbridge/amd/{agesa,pi}/hudson/lpc.c: Sync together by Edward O'Callaghan · 9 years ago
  2. d0e212c devicetree: Discriminate device ops scan_bus() by Kyösti Mälkki · 9 years ago
  3. 83f81ca acpi: Remove monolithic ACPI by Vladimir Serbinenko · 10 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 8d9a1bd southbridge/amd/pi: Add initialization of 8254 and 8259 by Dave Frodin · 9 years ago
  6. 5c015f0 southbridge/amd/pi: write_hpet requires additional config option by Dave Frodin · 10 years ago
  7. bc21a41 southbridge/amd/pi: Rename Avalon to Hudson by Dave Frodin · 10 years ago[Renamed from src/southbridge/amd/pi/avalon/lpc.c]
  8. 0b5b541 AMD binaryPI 00730F01: Switch to per-device ACPI by Kyösti Mälkki · 10 years ago
  9. 03abaee21 drivers/pc80/mc146818rtc: Assume we always have ALTCENTURY by Gabe Black · 10 years ago
  10. e8b4da2 AMD: Isolate AGESA and PI build environments for southbridge by Kyösti Mälkki · 10 years ago