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review.coreboot.org / coreboot / 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6 / src / soc / intel / alderlake / xhci.c
  1. c07d2e5 soc/intel/alderlake: Correct TCSS XHCI Port status offset by Sridhar Siricilla · 3 years, 3 months ago
  2. 291b58f soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support by Tim Wawrzynczak · 3 years, 9 months ago