- 43607e4 soc/intel/alderlake: Enable support for common IRQ block by Tim Wawrzynczak · 3 years, 3 months ago
- 6464c2a soc/intel/alderlake: Fix the typo for FSP_S_CONFIG param by V Sowmya · 3 years, 2 months ago
- b03cadf soc/intel/alderlake: Refactor soc_silicon_init_params function by Subrata Banik · 3 years, 2 months ago
- c0983c9 soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg by Subrata Banik · 3 years, 2 months ago
- 6f1cb40 soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function by Subrata Banik · 3 years, 2 months ago
- e633804 soc/intel/alderlake: Use devfn_disable() function for XDCI by Subrata Banik · 3 years, 2 months ago
- 095f97b soc/intel/alderlake: Add TBT PCIe root ports enablement by Bernardo Perez Priego · 3 years, 3 months ago
- 50134ec soc/intel/alderlake: Make use of is_devfn_enabled() function by Subrata Banik · 3 years, 2 months ago
- b9b6f4d soc/intel: Drop unused lpss functions by Furquan Shaikh · 3 years, 3 months ago
- 8e7facf soc/intel/alderlake: mb/intel/sm: Add tcss code by Deepti Deshatty · 3 years, 3 months ago
- 6935350 soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC by Maulik V Vaghela · 3 years, 4 months ago
- bc1941f soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry by Cliff Huang · 3 years, 6 months ago
- 812b54e soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selected by Ronak Kanabar · 3 years, 6 months ago
- 5b302b2 soc/intel/alderlake: Refactor PCIE port config by Eric Lai · 3 years, 9 months ago
- 85144d9 soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs by Subrata Banik · 3 years, 7 months ago
- 99289a8 soc/intel/alderlake: Update CPU microcode patch base address/size by Subrata Banik · 3 years, 8 months ago
- 2871e0e soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage by Subrata Banik · 3 years, 11 months ago