- a137201 soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities by Tim Wawrzynczak · 3 years, 4 months ago
- 8d3cc1b soc/intel/tigerlake: Add known GPIO virtual wire information by Tim Wawrzynczak · 3 years, 4 months ago
- 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
- ac95903 treewide: replace GPLv2 long form headers with SPDX header by Patrick Georgi · 4 years, 3 months ago
- 02363b5 treewide: Move "is part of the coreboot project" line in its own comment by Patrick Georgi · 4 years, 4 months ago
- 56e3df4 soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel by Shaunak Saha · 4 years, 5 months ago
- 555c9b6 soc/intel/tigerlake: Remove Jasper Lake SoC references by Aamir Bohra · 4 years, 5 months ago[Renamed from src/soc/intel/tigerlake/gpio_tgl.c]
- 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
- 1c2313d soc/intel/tigerlake: Add Jasper lake GPIO support by Ronak Kanabar · 4 years, 8 months ago[Renamed (98%) from src/soc/intel/tigerlake/gpio.c]
- e8338da soc/intel/tigerlake: Fix GPIO communities by Shaunak Saha · 4 years, 7 months ago
- 9d678f2 soc/intel/tigerlake: Update GPIO config by Ravi Sarawadi · 4 years, 8 months ago
- 91e89c5 soc/intel/tigerlake: Do initial SoC commit till ramstage by Subrata Banik · 4 years, 10 months ago